Xilinx 1000BASE-X Virtex-4 Devices

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 171

UG155 March 24, 2008

Required Constraints

INST "core_wrapper/tbi_rx_clk1_dcm" CLKOUT_PHASE_SHIFT = FIXED;

INST "core_wrapper/tbi_rx_clk1_dcm" PHASE_SHIFT = -10;

INST "core_wrapper/tbi_rx_clk1_dcm" DESKEW_ADJUST = 0;

The values of PHASE_SHIFT are preconfigured in the example designs to meet the setup

and hold constraints for the example TBI pinout in the particular device. The setup/hold

timing which is achieved after place-and-route is reported in the datasheet section of the

TRCE report (created by the implement script).

For customers fixing their own pinout, the setup and hold figures reported in the TRCE

report can be used to initially setup the approximate DCM phase shift values. Appendix C,

“Calculating the DCM Fixed Phase Shift Value” describes a more accurate method for

fixing the phase shift by using hardware measurement of a unique PCB design.

Virtex-4 Devices

Figure 6-4, page 73 illustrates the TBI input logic provided by the example design for the

Virtex-4 family. IDELAY elements are instantiated on the TBI data input path as illustrated:

the number of tap delays is currently set to zero. This can be modified in the UCF file, if

desired, to de-skew the bus for PCB routing.

A fixed tap delay is applied to delay the pma_rx_clk0 clock so that it correctly samples

the TBI data at the IOB IDDR register, thereby meeting TBI setup and hold timing.

The tap delays are applied using the following UCF syntax.

#-----------------------------------------------------------

# To Adjust TBI Rx Input Setup/Hold Timing -

#-----------------------------------------------------------

INST "core_wrapper/delay_pma_rx_clk" IOBDELAY_VALUE = "40";

INST "core_wrapper/tbi_rx_data_bus[9].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[8].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[7].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[6].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[5].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[4].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[3].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[2].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[1].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[0].delay_tbi_rx_data"

IOBDELAY_VALUE = "0";

The value of IOBDELAY_VALUE for the pma_rx_clk0 clock is preconfigured in the

example designs to meet the setup and hold constraints for the example TBI pinout in the

particular device. The setup/hold timing which is achieved after place-and-route is

reported in the datasheet section of the TRCE report (created by the implement script). See

“Understanding Timing Reports for Setup/Hold Timing.”