Xilinx 1000BASE-X Special Design Considerations, Power Management, Startup Sequencing, Loopback

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Chapter 14

Special Design Considerations

This chapter describes the unique design considerations associated with implementing the Ethernet 1000BASE-X PCS/PMA or SGMII core.

Power Management

No power management considerations are recommended for the Ethernet 1000BASE-X PCS/PMA or SGMII core when using it with the TBI. When using the Ethernet 1000BASE- X PCS/PMA or SGMII core with the Virtex-II Pro, the RocketIO transceiver may be placed in a low-power state in either of the following ways:

•Writing to the PCS Configuration Register 0 (if using the core with the optional Management Interface). The low-power state can only be removed by issuing the core with a reset. This reset can be achieved either by writing to the software reset bit in the PCS Configuration Register 0, or by driving the core reset port.

•Asserting the Power Down bit in the configuration_vector (if using the core without the optional Management Interface). The low-power state can only be removed by issuing the core with a reset by driving the reset port of the core.

Startup Sequencing

IEEE 802.3 clause 22.2.4.1.6 states that by default, a PHY should power-up in an isolate state (electrically isolated from the GMII).

•If you are using the core with the optional Management Interface, it is necessary to write to the PCS Configuration Register 0 to take the core out of the isolate state.

•If using the core without the optional Management interface, it is the responsibility of the client to ensure that the isolate input signal in the configuration_vector is asserted at power-on.

Loopback

This section details the implementation of the loopback feature. Loopback mode is enabled or disabled by either the “MDIO Management Interface,” page 115, or by the “Optional Configuration Vector,” page 151.

Core with the TBI

There is no physical loopback path in the core. Placing the core into loopback has the effect of asserting logic 1 on the ewrap signal of the TBI (see “1000BASE-X PCS with TBI Pinout,”

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 197

UG155 March 24, 2008