Xilinx manual Ethernet 1000BASE-X PCS/PMA or Sgmii 105

RocketIO Logic with the Fabric Rx Elastic Buffer

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Virtex-5 FXT Devices for SGMII or Dynamic Standards Switching

The core is designed to integrate with the Virtex-5 RocketIO GTX transceiver. The connections and logic required between the core and GTX transceiver are illustrated in Figure 8-6–the signal names and logic in the figure precisely match those delivered with the example design when a GTX transceiver is used.

Note: A small logic shim (included in the block” level wrapper) is required to convert between the port differences between the Virtex-II Pro and Virtex-5 RocketIO GTX transceiver. This is not illustrated in Figure 8-6.

A GTX tile consists of a pair of transceivers. For this reason, the GTX transceiver wrapper delivered with the core will always contain two GTX transceiver instantiations, even if only a single GTX is in use. Figure 8-6illustrates only a single GTX transceiver for clarity.

The 125 MHz differential reference clock is routed directly to the GTX transceiver. The GTX transceiver is configured to output a version of this clock on the REFCLKOUT port: this is then routed to a DCM.

From the DCM, the CLK0 port (125MHz) is placed onto global clock routing and can be used as the 125MHz clock source for all core logic: this clock is also input back into the GTX transceiver on the user interface clock port txusrclk2.

From the DCM, the CLKDV port (62.5MHz) is placed onto global clock routing and is input back into the GTX transceiver on the user interface clock port txusrclk.

It can be seen from Figure 8-6that the Rx Elastic Buffer is implemented in the FPGA fabric between the GTX transceiver and the core; this replaces the Rx Elastic Buffer in the GTX transceiver.

This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as large as the one present in the GTX transceiver. It is able to cope with larger frame sizes before clock tolerances accumulate and result in emptying or filling of the buffer. This is necessary to guarantee SGMII operation at 10 Mbps where each frame size is effectively 100 times larger than the same frame would be at 1 Gbps because each byte is repeated 100 times (see “Designing with Client-side GMII for the SGMII Standard,” page 59).

With this fabric Rx Elastic Buffer implementation, data is clocked out of the GTX transceiver synchronously to rxrecclk0 (62.5MHz) on a 16-bit interface. This clock can be placed on a BUFR component and is used to synchronize the transfer of data between the GTX and the Elastic Buffer, as illustrated in Figure 8-6. See also “Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards Switching Constraints,” page 168.

Virtex-5 RocketIO GTX Wizard

The two wrapper files immediately around the GTX transceiver pair,

rocketio_wrapper_gtx_tile and rocketio_wrapper_gtx (see Figure 8-6), are generated from the RocketIO GTP Wizard. These files apply all the gigabit Ethernet attributes. Consequently, these files can be regenerated by customers and therefore be easily targeted at ES or Production silicon. Note that this core targets production silicon.

The CORE Generator log file (XCO file) which was created when the RocketIO GTX Wizard project was generated is available in the following location:

<project_directory>/<component_name>/example_design/transceiver/ rocketio_wrapper_gtx.xco

This file can be used as an input to the CORE Generator to regenerate the RocketIO wrapper files. The XCO file itself contains a list of all of the GTX Wizard attributes which were used. For further information, please refer to the Virtex-5 RocketIO GTX Wizard

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 105

UG155 March 24, 2008