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Chapter 2: Core Architecture
1000BASE-X PCS with TBI Pinout
Table
Table
Signal | Direction | Clock Domain | Description |
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gtx_clk | Input | N/A | Clock signal at 125 MHz. Tolerance |
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| must be within IEEE 802.3 |
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| specification. |
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tx_code_group[9:0] | Output | gtx_clk | |
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| Sublayer (SERDES). |
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loc_ref | Output | N/A | Causes the PMA sublayer clock |
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| recovery unit to lock to pma_tx_clk. |
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| This signal is currently tied to Ground. |
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ewrap | Output | gtx_clk | When ’1,’ this indicates to the external |
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| PMA SERDES device to enter loopback |
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| mode. When ’0,’ this indicates normal |
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| operation |
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rx_code_group0[9:0] | Input | pma_rx_clk0 | |
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| Sublayer (SERDES). This is |
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| synchronous to pma_rx_clk0. |
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rx_code_group1[9:0] | Input | pma_rx_clk1 | |
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| Sublayer (SERDES). This is |
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| synchronous to pma_rx_clk1. |
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pma_rx_clk0 | Input | N/A | Received clock signal from PMA |
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| Sublayer (SERDES) at 62.5 MHz. |
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pma_rx_clk1 | Input | N/A | Received clock signal from PMA |
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| Sublayer (SERDES) at 62.5 MHz. This |
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| is 180 degrees out of phase with |
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| pma_rx_clk0. |
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en_cdet | Output | gtx_clk | Enables the PMA Sublayer to perform |
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| comma realignment. This is driven |
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| from the PCS Receive Engine during |
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| the |
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38 | www.xilinx.com | Ethernet |
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| UG155 March 24, 2008 |