Xilinx 1000BASE-X Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards Switching Constraints, Ten-Bit Interface Constraints

168 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

UG155 March 24, 2008

Chapter 12: Constraining the Core

NET "*clkin" TNM_NET = "clkin";

TIMESPEC "TS_clkin" = PERIOD "clkin" 8 ns HIGH 50 %;

NET "*refclkout" TNM_NET = "refclkout";

TIMESPEC "TS_refclkout" = PERIOD "refclkout" 8 ns HIGH 50 %;

The Virtex-5 GTX transceiver has many attributes that are set directly from HDL source

code for the transceiver wrapper file delivered with the example design. These can be

found in the rocketio_wrapper_gtx_tile.vhd file (for VHDL design entry) or the

rocketio_wrapper_gtx_tile.v file (for Verilog design entry): these files were

generated using the GTX Transceiver Wizard - to change the attributes, re-run the Wizard.

See “Virtex-5 RocketIO GTX Wizard” in Chapter 7.

Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards Switching Constraints

If the core is generated to use the GTX Rx Elastic Buffer, then all of the constraints

documented in “Clock Period Constraints,” page 167, apply.

However, if the FPGA Fabric Rx Elastic Buffer is selected, then an extra clock period

constraint of 16 ns is required for rxrecclk: with the GTX Rx Elastic Buffer bypassed,

rxrecclk is provided by the GTX transceiver to the FPGA fabric for the recovered

receiver data signals leaving the transceiver. This data is then written into the replacement

Rx Elastic Buffer implemented in the FPGA fabric. See “Virtex-5 FXT Devices for SGMII or

Dynamic Standards Switching,” page 105 for more information about this logic.

The following UCF syntax shows the necessary constraint being applied to the rxrecclk

signal sourced from GTX 0.

#***********************************************************

# PCS/PMA Clock period Constraints for the GTP/X 0 *

# recovered clock: please do not relax *

#***********************************************************

NET "core_wrapper/rocketio/rxrecclk0" TNM_NET = "rxrecclk0";

TIMESPEC "ts_rxrecclk0" = PERIOD "rxrecclk0" 16 ns;

Additionally, if the FPGA Fabric Rx Elastic Buffer is selected, then the attributes of the

Virtex-5 GTX transceiver which are set directly from HDL source code do differ from the

standard case. These can be found in the rocketio_wrapper_gtx_tile.vhd file (for

VHDL design entry) or the rocketio_wrapper_gtx_tile.v file (for Verilog design

entry): these files were generated using the GTX RocketIO Wizard - to change the

attributes, re-run the Wizard. See “Virtex-5 RocketIO GTX Wizard” in Chapter 8.

Ten-Bit Interface Constraints

The constraints defined in this section are implemented in the UCF for the example

designs delivered with the core. Sections from this UCF have been copied into the

descriptions in this section to serve as examples, and should be studied with the HDL

source code for the example design. See also Chapter 6, “The Ten-Bit Interface.”