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Preface: About This Guide
•Chapter 11, “Dynamic Switching of
•Chapter 12, “Constraining the Core” defines the constraint requirements of the core.
•Chapter 13, “Interfacing to Other Cores” describes additional design considerations associated with implementing the core with the
•Chapter 14, “Special Design Considerations” describes additional design considerations associated with implementing the core.
•Chapter 15, “Implementing the Design”describes how to simulate and implement your design containing the core.
•Appendix A, “Core Verification, Compliance, and Interoperability” describes how the core was verified.
•Appendix B, “Core Latency” defines the latency of the core.
•Appendix C, “Calculating the DCM Fixed Phase Shift Value” instructs the user about how to calculate the system timing requirements when using DCMs with the core.
•Appendix D,
•Appendix E, “Rx Elastic Buffer Specifications” describes the depth of the Rx Elastic Buffers which are available with the core. The size of the buffer is related to the maximum frame size which the core can accommodate.
•Appendix F, “Debugging Guide” provides information for debugging the core within a system.
Conventions
This document uses the following conventions. An example illustrates each convention.
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| UG155 March 24, 2008 |