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Preface
About This Guide
The LogiCORE™ IP Ethernet
Guide Contents
This guide contains the following information.
•Preface, “About This Guide” introduces the organization and purpose of this guide and defines the conventions used in this document.
•Chapter 1, “Introduction” describes the core and related information, including recommended design experience, additional documentation resources, technical support, and submitting feedback to Xilinx.
•Chapter 2, “Core Architecture” provides an overview of the core including all interfaces and major functional blocks.
•Chapter 3, “Generating and Customizing the Core” describes the Graphical User Interface (GUI) options used to generate and customize the core.
•Chapter 4, “Designing with the Core” provides general guidelines for creating designs with the core.
•Chapter 5, “Using the
•Chapter 6, “The
•Chapter 7,
•Chapter 8, “SGMII / Dynamic Standards Switching with RocketIO Transceivers” provides general design guidelines when using either the SGMII standard, or the Dynamic Switching option (between
•Chapter 9, “Configuration and Status” provides general guidelines for configuring and monitoring the core, including a detailed description of the management registers present in the core.
•Chapter 10,
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