Integrating with the Tri-Mode Ethernet MAC Core
R
Features of this configuration include:
•Direct internal connections are made between the GMII interfaces between the two cores.
•If both cores have been generated with the optional management interface, the MDIO port can be connected up to that of the
•Due to the embedded Receiver Elastic Buffer in the GTX transceiver, the entire GMII is synchronous to a single clock domain. Therefore userclk2 is used as the 125 MHz reference clock for both cores, and the transmitter and receiver logic of the
Integration of the
The connections required to provide SGMII functionality are identical to the connections required for either “Integration of the
Note: When operating at 1 Gbps speed only, the Rx Elastic Buffer internal to the GTP transceiver should be used to save device resources. Additionally, when operating at 1 Gbps only, the SGMII Adaptation Module instantiated from within the block level of the example design is not required and can optionally be removed.
Integrating with the Tri-Mode Ethernet MAC Core
The
A description of the latest available IP update containing the
www.xilinx.com/systemio/temac/index.htm
Caution! The
Integration of the
Figure 13-7 illustrates the connections and clock management logic required to interface the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in SGMII mode with the TBI) to the Tri-Mode Ethernet MAC core. The following is a description of the functionality.
•The SGMII Adaptation module, provided in the example design for the Ethernet 1000BASE-X PCS/PMA or SGMII core when generated to the SGMII standard, can be used to interface the two cores.
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