R
Chapter 14: Special Design Considerations
page 38). This instructs the attached PMA SERDES device to enter loopback mode as illustrated in Figure
FPGA
Ethernet
TBI
SERDES |
Loopback occurs in external SERDES
Tx
Rx
Figure 14-1: Loopback Implementation Using the TBI
Core with RocketIO Transceiver
The loopback path is implemented in the core as illustrated in Figure
Earlier versions (before v5.0) of the core implemented loopback differently. The serial loopback feature of the RocketIO transceiver was used by driving the LOOPBACK[1:0] port of the RocketIO (MGT or GTP) transceiver. This is no longer the case, and the loopback[1:0] output port of the core is now permanently set to logic “00.” However, for debugging purposes, the LOOPBACK[1:0] input port of the RocketIO transceiver may be directly driven by the user logic to place it in either parallel or serial loopback mode.
198 | www.xilinx.com | Ethernet |
|
| UG155 March 24, 2008 |