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Chapter 2: Core Architecture

Figure 2-4shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using a RocketIO transceiver without the optional PCS Management Registers

GMII gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

MDIO Replacement

configuration_vector[3:0]

reset gtx_clk

RocketIO Interface

mgt_rx_reset mgt_tx_reset

userclk userclk2 dcm_locked

rxbufstatus[1:0]

rxchariscomma rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0] rxdisperr rxnotintable

rxrundisp txbuferr

powerdown txchardispmode txchardispval txcharisk txdata enablealign

signal_detect

status_vector[4:0]

Figure 2-4:Component Pinout Using RocketIO Transceiver

without PCS Management Registers

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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

 

 

UG155 March 24, 2008

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Xilinx 1000BASE-X manual Core Architecture