Post-Implementation Simulation
R
layout and timing requirements specified within the PCF file. The par command outputs the placed and routed physical design to an NCD file.
An example of the par command is:
$ par top_level_module_name_map.ncd top_level_module_name.ncd \
top_level_module_name.pcf
Static Timing Analysis
The trce command must be executed to evaluate timing closure on a design and create a Timing Report file (TWR) that is derived from static timing analysis of the Physical Design file (NCD). The analysis is typically based on constraints included in the optional PCF file.
An example of the trce command is:
$ trce
top_level_module_name.pcf
Generating a Bitstream
The bitgen command must be executed to create the configuration bitstream (BIT) file based on the contents of a physical implementation file (NCD). The BIT file defines the behavior of the programmed FPGA.
An example of the bitgen command is:
$ bitgen
Post-Implementation Simulation
The purpose of
Generating a Simulation Model
To generate a
VHDL
$ netgen
Verilog
$ netgen
Using the Model
For information about setting up your simulator to use the
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