R
Appendix A
Core Verification, Compliance, and Interoperability
Verification
The Ethernet
Simulation
A highly parameterizable transaction based test bench was used to test the core. Testing included the following:
•Register Access
•Loss of Synchronization
•
•Frame Transmission and error handling
•Frame Reception and error handling
•Clock Compensation in the Elastic Buffers
Hardware Verification
The core has been tested in a variety of hardware test platforms at Xilinx to represent different parameterizations, including the following:
•The core with RocketIO transceiver and performing the
This follows the architecture shown in Figure
•The core with RocketIO transceiver (all supported families) and performing the SGMII standard was tested with the
This was connected to an external PHY capable of performing
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