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Chapter 13: Interfacing to Other Cores
•If both cores have been generated with the optional management interface, the MDIO port can be connected to that of the
•Due to the Receiver Elastic Buffer in the core, the entire GMII (transmitter and receiver paths) is synchronous to a single clock domain. Therefore, the txcoreclk and rxcoreclk inputs of the
Figure 13-7 illustrates the Tri-Mode Ethernet MAC core generated with the optional clock enable circuitry. This is the most efficient way to connect the two cores together in terms of clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for more information.
186 | www.xilinx.com | Ethernet |
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| UG155 March 24, 2008 |