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Appendix F
Debugging Guide
This appendix provides assistance for debugging the core within a system. For additional help, contact Xilinx by submitting a WebCase at support.xilinx.com/.
General Checks
•Ensure that all the timing constraints for the core were met during Place and Route.
•Does it work in timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue.
•Ensure that all clock sources are clean. If using DCMs in the design, ensure that all DCMs have obtained lock by monitoring the LOCKED port.
Problems with the MDIO
•Ensure that the MDIO is driven properly. See “MDIO Management Interface,” page 115 for detailed information about performing MDIO transactions.
•Check that the mdc clock is running and that the frequency is 2.5 MHz or less.
•Read from a configuration register that does not have all 0s as a default. If all 0s are read back, the read was unsuccessful. Check that the PHYAD field placed into the MDIO frame matches the value placed on the phyad[4:0] port of the core.
Problems with Data Reception or Transmission
When no data is being received or transmitted:
•Ensure that a valid link has been established between the core and its link partner, either by
♦“Problems with
♦“Problems in Obtaining a Link
Note: Transmission through the core is not allowed unless a link has been established. This behavior can be overridden by setting the Unidirectional Enable bit.
•Ensure that the Isolate state has been disabled.
By default, the Isolate state is enabled after
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