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Xilinx 1000BASE-X manual Debugging Guide, General Checks, Problems with the Mdio

Models: 1000BASE-X

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Appendix F

Debugging Guide

This appendix provides assistance for debugging the core within a system. For additional help, contact Xilinx by submitting a WebCase at support.xilinx.com/.

General Checks

•Ensure that all the timing constraints for the core were met during Place and Route.

•Does it work in timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue.

•Ensure that all clock sources are clean. If using DCMs in the design, ensure that all DCMs have obtained lock by monitoring the LOCKED port.

Problems with the MDIO

•Ensure that the MDIO is driven properly. See “MDIO Management Interface,” page 115 for detailed information about performing MDIO transactions.

•Check that the mdc clock is running and that the frequency is 2.5 MHz or less.

•Read from a configuration register that does not have all 0s as a default. If all 0s are read back, the read was unsuccessful. Check that the PHYAD field placed into the MDIO frame matches the value placed on the phyad[4:0] port of the core.

Problems with Data Reception or Transmission

When no data is being received or transmitted:

•Ensure that a valid link has been established between the core and its link partner, either by Auto-Negotiation or Manual Configuration: status_vector[0] and status_vector[1] should both be high. If no link has been established, see the topics discussed in the next section.

♦“Problems with Auto-Negotiation”

♦“Problems in Obtaining a Link (Auto-Negotiation Disabled)”

Note: Transmission through the core is not allowed unless a link has been established. This behavior can be overridden by setting the Unidirectional Enable bit.

•Ensure that the Isolate state has been disabled.

By default, the Isolate state is enabled after power-up. For an external GMII, the PHY will be electrically isolated from the GMII; for an internal GMII, it will behave as if it is isolated. This results in no data transfer across the GMII. See “Startup Sequencing,” page 197 for more information.

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

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UG155 March 24, 2008

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Xilinx 1000BASE-X Debugging Guide, General Checks, Problems with the Mdio, Problems with Data Reception or Transmission

Contents

UG155 March 24 LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SgmiiDate Doc Revision Version Revision HistoryTable of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 Schedule of Figures 1Functional Block Diagram Using RocketIO TransceiverAuto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 Schedule of Tables 5Optional Auto-Negotiation Interface Signal Pinout33SGMII Auto-Negotiation Advertisement Register 4 About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideConventions Meaning or Use Example Online DocumentPreface About This Guide Recommended Design Experience Designs Using RocketIO TransceiversIntroduction About the CoreEthernet 1000BASE-X PCS/PMA or Sgmii Core Additional Core ResourcesTechnical Support FeedbackFeedback DocumentIntroduction System Overview Core ArchitectureOptional Auto-Negotiation Block Gmii BlockPCS Transmit Engine PCS Receive Engine and SynchronizationSystem Overview Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceOptional PCS Management Registers RocketIO Interface BlockReceiver Elastic Buffer Core Interfaces8B/10B Encoder 8B/10B DecoderCore Interfaces Core Architecture Core Interfaces Core Architecture Gmii Pinout Client Side InterfaceEthernet 1000BASE-X PCS/PMA or Sgmii 2Other Common Signals Direction Description Common Signal PinoutMAC Mdio Management Interface Pinout Optional5Optional Auto-Negotiation Interface Signal Pinout Configuration Vector OptionalAuto-Negotiation Signal Pinout Physical Side Interface Dynamic Switching Signal PinoutEthernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Component Name Generating and Customizing the CoreGUI Interface Generating and Customizing the Core Select StandardCore Functionality Auto-Negotiation SGMII/Dynamic Standard Switching Elastic Buffer OptionsPhysical Interface Mdio Management Interface3SGMII/Dynamic Standard Switching Options Screen Parameter Values in the XCO File RocketIO Tile ConfigurationParameter Values in the XCO File TBI Output GenerationDesign Overview Designing with the CoreDesigning with the Core Design Overview 1000BASE-X Standard with TBI Example DesignExample Design Performing the Sgmii Standard Sgmii Standard Using a RocketIO Transceiver Example Design4Example Design Performing the Sgmii Standard Sgmii Standard with TBI Transceiver Example DesignExamine the Example Design Provided with the Core Design GuidelinesGenerate the Core Simulate and Download your Design Write an HDL ApplicationSynthesize your Design Create a BitstreamMake Only Allowed Modifications Recognize Timing Critical SignalsKeep it Registered Use Supported Design FlowsNormal Frame Transmission Using the Client-side Gmii Data PathGmii Transmission Normal Frame Reception Error PropagationUsing the Client-side Gmii Data Path Gmii ReceptionNormal Frame Reception with Extension Field Frame Reception with ErrorsBit1 Link Synchronization Statusvector40 signalsFalse Carrier Bit0 Link StatusGmii Transmission Bits42 Code Group Reception IndicatorsGmii Reception Megabit per Second Frame Transmission Designing with Client-side Gmii for the Sgmii StandardOverview Gigabit per Second Frame TransmissionMegabit per Second Frame Reception Gigabit per Second Frame ReceptionGmii Transmitter Logic Using the Gmii as an Internal ConnectionUsing the Gmii as an Internal Connection Implementing External Gmii14GMII Transmitter Logic Virtex-II Pro and Virtex-II DevicesImplementing External Gmii Spartan-3, Spartan-3E and Spartan-3A Devices16External Gmii Transmitter Logic for Virtex-4 Devices Virtex-4 Devices17External Gmii Transmitter Logic for Virtex-5 Devices Virtex-5 DevicesGmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Transmitter Logic Ten-Bit InterfaceTen-Bit-Interface Logic Ten-Bit Interface Receiver LogicVirtex-II and Virtex-II Pro Devices 2Ten-Bit-Interface Receiver Logic Ten-Bit-Interface LogicComponentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBITen-Bit Interface Virtex-II Pro Devices 1000BASE-X with RocketIO TransceiversRocketIO Transceiver Logic 11000BASE-X Connection to a Virtex-II Pro MGT 1000BASE-X with RocketIO TransceiversRocketIO Transceiver Logic Virtex-4 FX Devices21000BASE-X Connection to Virtex-4 MGT Virtex-5 RocketIO GTP Wizard Virtex-5 LXT and SXT Devices31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 RocketIO GTX Wizard Virtex-5 FXT Devices41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIOVirtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Selecting the Buffer Implementation from the GUI Receiver Elastic Buffer ImplementationsAnalysis Requirement for the Fpga Fabric Rx Elastic BufferReceiver Elastic Buffer Implementations RocketIO Rx Elastic BufferClosely Related Clock Sources RocketIO Logic using the RocketIO Rx Elastic BufferRocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Mdio Bus System Configuration and StatusMdio Management Interface 1Abbreviations and Terms Configuration and StatusMdio Transactions Mdio Management Interface 1Abbreviations and Terms Mdio AddressingWrite Transaction Read TransactionConnecting the Mdio to an External STA Connecting the Mdio to an Internally Integrated STA2MDIO Registers for 1000BASE-X with Auto-Negotiation 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers Management Registers3Control Register Register Register 0 Control RegisterMdio Register 0 Control Register LSB Management Registers 3Control Register Register4Status Register Register Register 1 Status RegisterMdio Register 1 Status Register Registers 2 and 3 PHY Identifiers Registers 2 and 3 PHY IdentifiersManagement Registers 4Status Register Register Auto-Negotiation Advertisement Register Register Configuration and Status 5PHY Identifier Registers 2Register 4 Auto-Negotiation Advertisement Mdio Register 4 Auto-Negotiation AdvertisementMdio Register 5 Auto-Negotiation Link Partner Base Register 5 Auto-Negotiation Link Partner Base8Auto-Negotiation Expansion Register Register Register 6 Auto-Negotiation ExpansionRegister 7 Next Page Transmit Mdio Register 6 Auto-Negotiation Expansion10Auto-Negotiation Next Page Receive Register Register 8 Next Page ReceiveMdio Register 8 Next Page Receive 11Extended Status Register Register Register 15 Extended StatusMdio Register 15 Extended Status Register 13MDIO Registers for 1000BASE-X without Auto-Negotiation 1000BASE-X Standard Without the Optional Auto-Negotiation14Control Register Register 15Status Register Register Management Registers 14Control Register RegisterConfiguration and Status 15Status Register Register Mdio Register 15 Extended Status Registers 2 and 3 Phy IdentifierMdio Registers 2 and 3 PHY Identifier 16PHY Identifier Registers 2Configuration and Status 17Extended Status Register Mdio Register 0 Sgmii Control Sgmii Standard Using the Optional Auto-NegotiationRegister 0 Sgmii Control 18MDIO Registers for 1000BASE-X with Auto-NegotiationConfiguration and Status 19SGMII Control Register 20SGMII Status Register Register 1 Sgmii StatusManagement Registers 19SGMII Control Register Mdio Register 1 Sgmii StatusConfiguration and Status 20SGMII Status Register 22SGMII Auto-Negotiation Advertisement Register Register 4 Sgmii Auto-Negotiation Advertisement21PHY Identifier Registers 2 Mdio Register 4 Sgmii Auto-Negotiation AdvertisementMdio Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 5 Sgmii Auto-Negotiation Link Partner AbilityRegister 7 Sgmii Auto-Negotiation Next Page Transmit Register 6 Sgmii Auto-Negotiation Expansion26SGMII Auto-Negotiation Next Page Receive Register Register 8 Sgmii Next Page ReceiveMdio Register 8 Sgmii Next Page Receive 27SGMII Extended Status Register Register Register 15 Sgmii Extended StatusMdio Register 15 Sgmii Extended Status 28SGMII Auto-Negotiation Interrupt Control Register Register 16 Sgmii Auto-Negotiation Interrupt ControlMdio Register 16 Sgmii Auto-Negotiation Interrupt Control 29MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard without the Optional Auto-NegotiationConfiguration and Status 30SGMII Control Register 31SGMII Status Register Management Registers 30SGMII Control RegisterConfiguration and Status 31SGMII Status Register 33SGMII Auto-Negotiation Advertisement Register 32PHY Identifier Registers 234SGMII Extended Status Register Register Both 1000BASE-X and Sgmii StandardsRegister 17 Vendor-specific Standard Selection Register Optional Configuration VectorOptional Configuration Vector Signal Direction Clock Description Domain 36Optional Configuration and Status VectorsOverview of Operation Auto-NegotiationAuto-Negotiation Sgmii Auto-Negotiation Sgmii StandardOverview of Operation Simulating Auto-Negotiation Setting the Configurable Link TimerUsing the Auto-Negotiation Interrupt 1000BASE-X StandardTypical Application Dynamic Switching of 1000BASE-X and Sgmii StandardsOperation of the Core Selecting the Power-On / Reset StandardSwitching the Standard Using Mdio Setting the Auto-Negotiation Link TimerOperation of the Core 160 Required Constraints Constraining the CoreConstraining the Core Setting MGT AttributesMGT Transceiver Placement Constraints Clock Period Constraints# Enmcommaalign Required Constraints1Local Clock Place and Route for Top MGT Virtex-4 RocketIO MGTs for 1000BASE-X ConstraintsMGT Placement Constraints Setting MGT Transceiver AttributesSetting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Ten-Bit Interface Constraints Setting GTX Transceiver AttributesTen-Bit Interface IOB Constraints 1Input TBI Timing Symbol Min Max Units TBI Input Setup/Hold TimingVirtex-4 Devices Virtex-5 Devices Constraints When Implementing an External GmiiGmii IOB Constraints 2Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold TimingEthernet 1000BASE-X PCS/PMA or Sgmii 175 Virtex-4 or Virtex-5 Devices Understanding Timing Reports for Setup/Hold TimingDevices Other Than Virtex-4 or Virtex-5 4Timing Report Setup/Hold Illustration 178 Integrating with the 1-Gigabit Ethernet MAC Core Interfacing to Other CoresMAC Interfacing to Other CoresIntegrating with the 1-Gigabit Ethernet MAC Core Virtex-II Pro Devices182 GTP Virtex-5 LXT and SXT DevicesClkdv Virtex-5 FXT DevicesIntegrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Loopback Power ManagementSpecial Design Considerations Startup SequencingSpecial Design Considerations Core with RocketIO TransceiverLoopback 200 Synthesis Using the Simulation ModelImplementing the Design Pre-implementation SimulationMapping the Design ImplementationXST Verilog Generating the Xilinx NetlistGenerating a Bitstream Using the ModelPost-Implementation Simulation Static Timing AnalysisVirtex-5 Devices Other Implementation InformationHardware Verification Core Verification, Compliance, and InteroperabilityVerification Simulation206 Transmit Path Latency Core LatencyCore Latency Latency for 1000BASE-X PCS with TBILatency for Sgmii Finding the Ideal Phase Shift Value for Your System Calculating the DCM Fixed Phase Shift ValueRequirement for DCM Phase Shifting Appendix C Calculating the DCM Fixed Phase Shift Value Introduction 1000BASE-X State MachinesAppendix D 1000BASE-X State Machines Start of Frame EncodingEven Transmission Case Start of Frame Encoding Reception of the Even CaseOdd Transmission Case Reception of the Odd Case End of Frame Encoding End of Frame EncodingPreamble Shrinkage 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 RocketIO Rx Elastic Buffers Rx Elastic Buffer SpecificationsRx Elastic Buffers Depths and Maximum Frame Sizes Virtex-II Pro and Virtex-5 Devices Appendix E Rx Elastic Buffer SpecificationsRx Elastic Buffers Depths and Maximum Frame Sizes Virtex-4 FXFigure E-2Elastic Buffer Size for all RocketIO families Sgmii Fabric Rx Elastic BufferFor 1000BASE-X For Sgmii / Dynamic SwitchingTBI Rx Elastic Buffer Idle Character Removal at 1Gbps 1000BASE-X and Sgmii Clock CorrectionClock Correction Idle Character Removal at 100 Mbps SgmiiIdle Character Removal at 10 Mbps Sgmii RocketIO Sgmii Fabric Buffer Maximum Frame Sizes for Sustained Frame ReceptionJumbo Frame Reception General Checks Problems with the MdioProblems with Data Reception or Transmission Debugging GuideAppendix F Debugging Guide Problems with Auto-NegotiationProblems in Obtaining a Link Auto-Negotiation Disabled Debugging Problems with a High Bit Error RateSymptoms Problems with a High Bit Error RateRocketIO Transceiver Specific Checks