R
Appendix B
Core Latency
Core Latency
The standalone core does not meet all the latency requirements specified in IEEE 802.3 due to the latency of the Elastic Buffers in both TBI and RocketIO transceiver versions. However, the core may be used for backplane and other applications where strict adherence to the IEEE latency specification is not required.
Where strict adherence to the IEEE 802.3 specification is required, the core may be used with an Ethernet MAC core that is within the IEEE specified latency for a MAC sublayer. For example, when the core is connected to the Xilinx
Latency for 1000BASE-X PCS with TBI
The following measurements are for the core only, and do not include any IOB registers or the Transmitter Elastic Buffer added in the example design.
Transmit Path Latency
As measured from a data octet input into gmii_txd[7:0] of until that data appears on tx_code_group[9:0] on the TBI through the core in the transmit direction is 5 clock periods of
the transmitter side GMII interface, the latency gtx_clk.
Receive Path Latency
Measured from a data octet input into the core on rx_code_group0[9:0] or rx_code_group1[9:0] from the TBI interface (until that data appears on gmii_rxd[7:0] of the receiver side GMII), the latency through the core in the receive direction is equal to 16 clock periods of gtx_clk, plus an additional number of clock cycles equal to the current value of the Receiver Elastic Buffer.
The Receiver Elastic Buffer is 32 words deep. The nominal occupancy will be at
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