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Chapter 13
Interfacing to Other Cores
This chapter describes some additional design considerations associated with implementing the Ethernet
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Integrating with the 1-Gigabit Ethernet MAC Core
The
A description of and instructions for obtaining the newest
www.xilinx.com/systemio/gmac/index.htm
Integration of the
Figure 13-1 illustrates the connections and clock management logic required to interface the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode with the parallel TBI) to the 1-Gigabit Ethernet MAC core.
Features of this configuration include:
•Direct internal connections are made between the GMII interfaces between the two cores.
•If both cores have been generated with the optional management interface, the MDIO port can be connected to that of the 1-Gigabit Ethernet MAC core, allowing the MAC to access the embedded configuration and status registers of the Ethernet 1000BASE-X PCS/PMA or SGMII core.
•Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE-X PCS/PMA, the entire GMII is synchronous to a single clock domain. Therefore, gtx_clk is used as the 125 MHz reference clock for both cores, and the transmitter and receiver logic of the 1-Gigabit Ethernet MAC core operates in the same clock domain.
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