R
Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
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| brefclkp | GT11CLK_MGT |
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| (250MHz) |
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| IPAD | MGTCLKP |
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| IPAD | MGTCLKN |
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| brefclkn | |
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| BUFG | (250MHz) | synclk1 |
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| (250MHz) |
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| SYNCLK1OUT |
component_name_block |
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(Block Level) |
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| MGT tile |
Ethernet |
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PCS/PMA or |
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SGMII core |
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| GT11 |
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| RocketIO |
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| (A) |
| userclk2 |
| TXOUTCLK1 |
userclk |
| REFCLK1 | |
(125 MHz) |
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userclk2 |
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| TXUSRCLK | |
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| ‘0’ | |
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| TXUSRCLK2 |
| FPGA | ‘0’ | RXUSRCLK |
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| fabric |
| RXUSRCLK2 |
| Rx |
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| Elastic |
| RXRECCLK1 |
| Buffer |
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Ethernet |
| BUFR | |
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PCS/PMA or |
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| GT11 |
SGMII core |
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| RocketIO |
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| (B) |
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| NC | TXOUTCLK1 |
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| REFCLK1 |
userclk |
| ‘0’ | TXUSRCLK |
userclk2 |
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| TXUSRCLK2 |
| FPGA | ‘0’ | RXUSRCLK |
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| fabric |
| RXUSRCLK2 |
| Rx |
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| Elastic |
| RXRECCLK1 |
| Buffer |
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| BUFR |
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component_name_block |
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(Block Level) |
| MGT tile | |
Ethernet |
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PCS/PMA or |
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SGMII core |
| GT11 | |
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| RocketIO | |
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| (A) | |
| NC | TXOUTCLK1 | |
userclk | userclk2 | REFCLK1 | |
(125 MHz) | |||
userclk2 | |||
| TXUSRCLK | ||
| ‘0’ | ||
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| TXUSRCLK2 | |
| ‘0’ | RXUSRCLK | |
| FPGA |
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| fabric | RXUSRCLK2 | |
| Rx |
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| Elastic | RXRECCLK1 | |
| Buffer | ||
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Ethernet | BUFR | ||
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PCS/PMA or |
| GT11 | |
SGMII core |
| RocketIO | |
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| (B) | |
| NC | TXOUTCLK1 | |
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| REFCLK1 | |
userclk | ‘0’ | TXUSRCLK | |
userclk2 | |||
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| TXUSRCLK2 | |
| ‘0’ | RXUSRCLK | |
| FPGA |
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| fabric | RXUSRCLK2 | |
| Rx |
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| Elastic | RXRECCLK1 | |
| Buffer | ||
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| BUFR |
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Figure 8-8: Clock Management with Multiple Core Instances with Virtex-4 MGTs for
SGMII
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