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Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
Getting Started Guide and the CORE Generator Guide, at
www.xilinx.com/support/software_manuals.htm
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DCM BUFG
CLKIN CLK0 | userclk2 |
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brefclkp IBUFGDS
IPAD
FB CLKDV | userclk |
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BUFG
IPADclkin
brefclkn (125MHz)
rocketio_wrapper_gtp
component_name_block (Block Level from example design)
Ethernet
PCS/PMA or SGMII
LogiCORE
userclk
rocketio_wrapper_gtp_tile
GTP
RocketIO
(used)
CLKIN
REFCLKOUT
TXUSRCLK20
TXUSRCLK0
userclk2 |
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rxnotintable |
| FPGA |
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rxchariscomma |
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rxbufstatus[1:0] |
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rxcharisk |
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| Buffer |
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rxclkcorcnt[2:0] |
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rxdata[7:0] |
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rxrundisp |
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rxdisperr |
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| RXUSRCLK0 | |
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| RXUSRCLK20 |
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powerdown |
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txchardispmode |
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txchardispval |
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txcharisk |
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txdata[7:0] |
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enablealign |
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| RXENPCOMMAALIGN0 | ||
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| RXENMCOMMAALIGN0 |
Figure 8-6: SGMII Connection to a Virtex-5 RocketIO GTX Transceiver
106 | www.xilinx.com | Ethernet |
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| UG155 March 24, 2008 |