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Xilinx 1000BASE-X manual 216

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Appendix D: 1000BASE-X State Machines

Reception of the Even Case

Figure D-6illustrates the reception of the in-bound code-group stream, received either serially using the RocketIO transceiver, or in parallel across the TBI, and translation of this code-group stream into the receiver GMII. This is performed by the PCS Receive Engine.

rx_code_group

FCS

T R I1/I2 I2

I2

I2

PCS Receive Engine Decoding

gmii_rxd[7:0]	FCS
gmii_rx_dv
gmii_rx_er

Figure D-6:1000BASE-X Reception State Machine Operation (Even Case)

The Odd Transmission Case

Figure D-7illustrates the translation of GMII encoding into the code-group stream performed by the PCS Transmit Engine; this stream is transmitted out of the core, either serially using the RocketIO transceiver, or in parallel across the TBI.

In response to the deassertion of gmii_tx_en, an End of Packet code group /T/ is immediately inserted. Note that the even and odd alignment described in “Start of Frame Encoding” persists throughout the Ethernet frame. If the /T/ character occurs in the odd position (the frame contained an odd number of bytes starting from the /S/ character), then this is followed with two Carrier Extend code groups /R/. This allows the /K28.5/ character of the following Idle code group to be aligned to the even position.

216	www.xilinx.com	Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
		UG155 March 24, 2008

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Xilinx 1000BASE-X manual 216

Contents

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or Sgmii UG155 March 24Revision History Date Doc Revision VersionTable of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 1Functional Block Diagram Using RocketIO Transceiver Schedule of FiguresAuto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 5Optional Auto-Negotiation Interface Signal Pinout Schedule of Tables33SGMII Auto-Negotiation Advertisement Register 4 Guide Contents About This GuideConventions TypographicalPreface About This Guide Convention Meaning or Use ExampleOnline Document Conventions Meaning or Use ExamplePreface About This Guide Designs Using RocketIO Transceivers IntroductionAbout the Core Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback Ethernet 1000BASE-X PCS/PMA or Sgmii CoreDocument FeedbackIntroduction Core Architecture System OverviewGmii Block PCS Transmit EnginePCS Receive Engine and Synchronization Optional Auto-Negotiation BlockEthernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-Interface Optional PCS Management RegistersRocketIO Interface Block System OverviewCore Interfaces 8B/10B Encoder8B/10B Decoder Receiver Elastic BufferCore Interfaces Core Architecture Core Interfaces Core Architecture Client Side Interface Gmii PinoutEthernet 1000BASE-X PCS/PMA or Sgmii Common Signal Pinout 2Other Common Signals Direction DescriptionMdio Management Interface Pinout Optional MACConfiguration Vector Optional Auto-Negotiation Signal Pinout5Optional Auto-Negotiation Interface Signal Pinout Dynamic Switching Signal Pinout Physical Side InterfaceEthernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Generating and Customizing the Core GUI InterfaceComponent Name Select Standard Core FunctionalityGenerating and Customizing the Core SGMII/Dynamic Standard Switching Elastic Buffer Options Physical InterfaceMdio Management Interface Auto-Negotiation3SGMII/Dynamic Standard Switching Options Screen RocketIO Tile Configuration Parameter Values in the XCO FileParameter Values in the XCO File Output Generation TBIDesigning with the Core Design OverviewDesigning with the Core 1000BASE-X Standard with TBI Example Design Design OverviewSgmii Standard Using a RocketIO Transceiver Example Design Example Design Performing the Sgmii StandardSgmii Standard with TBI Transceiver Example Design 4Example Design Performing the Sgmii StandardDesign Guidelines Generate the CoreExamine the Example Design Provided with the Core Write an HDL Application Synthesize your DesignCreate a Bitstream Simulate and Download your DesignRecognize Timing Critical Signals Keep it RegisteredUse Supported Design Flows Make Only Allowed ModificationsUsing the Client-side Gmii Data Path Gmii TransmissionNormal Frame Transmission Error Propagation Using the Client-side Gmii Data PathGmii Reception Normal Frame ReceptionFrame Reception with Errors Normal Frame Reception with Extension FieldStatusvector40 signals False CarrierBit0 Link Status Bit1 Link SynchronizationBits42 Code Group Reception Indicators Gmii TransmissionGmii Reception Designing with Client-side Gmii for the Sgmii Standard OverviewGigabit per Second Frame Transmission Megabit per Second Frame TransmissionGigabit per Second Frame Reception Megabit per Second Frame ReceptionUsing the Gmii as an Internal Connection Using the Gmii as an Internal ConnectionImplementing External Gmii Gmii Transmitter LogicVirtex-II Pro and Virtex-II Devices 14GMII Transmitter LogicSpartan-3, Spartan-3E and Spartan-3A Devices Implementing External GmiiVirtex-4 Devices 16External Gmii Transmitter Logic for Virtex-4 DevicesVirtex-5 Devices 17External Gmii Transmitter Logic for Virtex-5 DevicesGmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Ten-Bit Interface Ten-Bit-Interface LogicTransmitter Logic Receiver Logic Virtex-II and Virtex-II Pro DevicesTen-Bit Interface Ten-Bit-Interface Logic 2Ten-Bit-Interface Receiver LogicComponentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBITen-Bit Interface 1000BASE-X with RocketIO Transceivers RocketIO Transceiver LogicVirtex-II Pro Devices 1000BASE-X with RocketIO Transceivers 11000BASE-X Connection to a Virtex-II Pro MGTVirtex-4 FX Devices RocketIO Transceiver Logic21000BASE-X Connection to Virtex-4 MGT Virtex-5 LXT and SXT Devices Virtex-5 RocketIO GTP Wizard31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 FXT Devices Virtex-5 RocketIO GTX Wizard41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIOVirtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Receiver Elastic Buffer Implementations Selecting the Buffer Implementation from the GUIRequirement for the Fpga Fabric Rx Elastic Buffer AnalysisRocketIO Rx Elastic Buffer Receiver Elastic Buffer ImplementationsRocketIO Logic using the RocketIO Rx Elastic Buffer Closely Related Clock SourcesRocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Configuration and Status Mdio Management InterfaceMdio Bus System Configuration and Status Mdio Transactions1Abbreviations and Terms Mdio Addressing Write TransactionRead Transaction Mdio Management Interface 1Abbreviations and TermsConnecting the Mdio to an Internally Integrated STA Connecting the Mdio to an External STA1000BASE-X Standard Using the Optional Auto-Negotiation Management RegistersManagement Registers 2MDIO Registers for 1000BASE-X with Auto-NegotiationRegister 0 Control Register Mdio Register 0 Control Register3Control Register Register Management Registers 3Control Register Register LSBRegister 1 Status Register Mdio Register 1 Status Register4Status Register Register Registers 2 and 3 PHY Identifiers Management Registers 4Status Register RegisterRegisters 2 and 3 PHY Identifiers Configuration and Status 5PHY Identifier Registers 2 Register 4 Auto-Negotiation AdvertisementMdio Register 4 Auto-Negotiation Advertisement Auto-Negotiation Advertisement Register RegisterRegister 5 Auto-Negotiation Link Partner Base Mdio Register 5 Auto-Negotiation Link Partner BaseRegister 6 Auto-Negotiation Expansion Register 7 Next Page TransmitMdio Register 6 Auto-Negotiation Expansion 8Auto-Negotiation Expansion Register RegisterRegister 8 Next Page Receive Mdio Register 8 Next Page Receive10Auto-Negotiation Next Page Receive Register Register 15 Extended Status Mdio Register 15 Extended Status Register11Extended Status Register Register 1000BASE-X Standard Without the Optional Auto-Negotiation 13MDIO Registers for 1000BASE-X without Auto-Negotiation14Control Register Register Management Registers 14Control Register Register 15Status Register RegisterConfiguration and Status 15Status Register Register Registers 2 and 3 Phy Identifier Mdio Registers 2 and 3 PHY Identifier16PHY Identifier Registers 2 Mdio Register 15 Extended StatusConfiguration and Status 17Extended Status Register Sgmii Standard Using the Optional Auto-Negotiation Register 0 Sgmii Control18MDIO Registers for 1000BASE-X with Auto-Negotiation Mdio Register 0 Sgmii ControlConfiguration and Status 19SGMII Control Register Register 1 Sgmii Status Management Registers 19SGMII Control RegisterMdio Register 1 Sgmii Status 20SGMII Status RegisterConfiguration and Status 20SGMII Status Register Register 4 Sgmii Auto-Negotiation Advertisement 21PHY Identifier Registers 2Mdio Register 4 Sgmii Auto-Negotiation Advertisement 22SGMII Auto-Negotiation Advertisement RegisterRegister 5 Sgmii Auto-Negotiation Link Partner Ability Mdio Register 5 Sgmii Auto-Negotiation Link Partner AbilityRegister 6 Sgmii Auto-Negotiation Expansion Register 7 Sgmii Auto-Negotiation Next Page TransmitRegister 8 Sgmii Next Page Receive Mdio Register 8 Sgmii Next Page Receive26SGMII Auto-Negotiation Next Page Receive Register Register 15 Sgmii Extended Status Mdio Register 15 Sgmii Extended Status27SGMII Extended Status Register Register Register 16 Sgmii Auto-Negotiation Interrupt Control Mdio Register 16 Sgmii Auto-Negotiation Interrupt Control28SGMII Auto-Negotiation Interrupt Control Register Sgmii Standard without the Optional Auto-Negotiation 29MDIO Registers for 1000BASE-X with Auto-NegotiationConfiguration and Status 30SGMII Control Register Management Registers 30SGMII Control Register 31SGMII Status RegisterConfiguration and Status 31SGMII Status Register 32PHY Identifier Registers 2 33SGMII Auto-Negotiation Advertisement RegisterBoth 1000BASE-X and Sgmii Standards 34SGMII Extended Status Register RegisterOptional Configuration Vector Optional Configuration VectorRegister 17 Vendor-specific Standard Selection Register 36Optional Configuration and Status Vectors Signal Direction Clock Description DomainAuto-Negotiation Overview of OperationAuto-Negotiation Sgmii Standard Overview of OperationSgmii Auto-Negotiation Setting the Configurable Link Timer Using the Auto-Negotiation Interrupt1000BASE-X Standard Simulating Auto-NegotiationDynamic Switching of 1000BASE-X and Sgmii Standards Typical ApplicationSelecting the Power-On / Reset Standard Switching the Standard Using MdioSetting the Auto-Negotiation Link Timer Operation of the CoreOperation of the Core 160 Constraining the Core Required ConstraintsSetting MGT Attributes MGT Transceiver Placement ConstraintsClock Period Constraints Constraining the CoreRequired Constraints # EnmcommaalignVirtex-4 RocketIO MGTs for 1000BASE-X Constraints 1Local Clock Place and Route for Top MGTSetting MGT Transceiver Attributes MGT Placement ConstraintsSetting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Setting GTX Transceiver Attributes Ten-Bit Interface ConstraintsTen-Bit Interface IOB Constraints TBI Input Setup/Hold Timing 1Input TBI Timing Symbol Min Max UnitsVirtex-4 Devices Constraints When Implementing an External Gmii Virtex-5 DevicesGmii IOB Constraints Gmii Input Setup/Hold Timing 2Input Gmii Timing Symbol Min Max UnitsEthernet 1000BASE-X PCS/PMA or Sgmii 175 Understanding Timing Reports for Setup/Hold Timing Devices Other Than Virtex-4 or Virtex-5Virtex-4 or Virtex-5 Devices 4Timing Report Setup/Hold Illustration 178 Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC CoreInterfacing to Other Cores MACVirtex-II Pro Devices Integrating with the 1-Gigabit Ethernet MAC Core182 Virtex-5 LXT and SXT Devices GTPVirtex-5 FXT Devices ClkdvIntegrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Power Management Special Design ConsiderationsStartup Sequencing LoopbackCore with RocketIO Transceiver Special Design ConsiderationsLoopback 200 Using the Simulation Model Implementing the DesignPre-implementation Simulation SynthesisImplementation XST VerilogGenerating the Xilinx Netlist Mapping the DesignUsing the Model Post-Implementation SimulationStatic Timing Analysis Generating a BitstreamOther Implementation Information Virtex-5 DevicesCore Verification, Compliance, and Interoperability VerificationSimulation Hardware Verification206 Core Latency Core LatencyLatency for 1000BASE-X PCS with TBI Transmit Path LatencyLatency for Sgmii Calculating the DCM Fixed Phase Shift Value Requirement for DCM Phase ShiftingFinding the Ideal Phase Shift Value for Your System Appendix C Calculating the DCM Fixed Phase Shift Value 1000BASE-X State Machines IntroductionStart of Frame Encoding Even Transmission CaseAppendix D 1000BASE-X State Machines Reception of the Even Case Odd Transmission CaseStart of Frame Encoding Reception of the Odd Case End of Frame Encoding Preamble ShrinkageEnd of Frame Encoding 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 Rx Elastic Buffer Specifications Rx Elastic Buffers Depths and Maximum Frame SizesRocketIO Rx Elastic Buffers Appendix E Rx Elastic Buffer Specifications Virtex-II Pro and Virtex-5 DevicesVirtex-4 FX Rx Elastic Buffers Depths and Maximum Frame SizesSgmii Fabric Rx Elastic Buffer Figure E-2Elastic Buffer Size for all RocketIO familiesFor Sgmii / Dynamic Switching TBI Rx Elastic BufferFor 1000BASE-X Clock Correction Idle Character Removal at 1Gbps 1000BASE-X and SgmiiIdle Character Removal at 100 Mbps Sgmii Idle Character Removal at 10 Mbps SgmiiClock Correction Maximum Frame Sizes for Sustained Frame Reception Jumbo Frame ReceptionRocketIO Sgmii Fabric Buffer Problems with the Mdio Problems with Data Reception or TransmissionDebugging Guide General ChecksProblems with Auto-Negotiation Problems in Obtaining a Link Auto-Negotiation DisabledAppendix F Debugging Guide Problems with a High Bit Error Rate SymptomsProblems with a High Bit Error Rate DebuggingRocketIO Transceiver Specific Checks