Xilinx 1000BASE-X manual Constraints When Implementing an External Gmii, Virtex-5 Devices

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Chapter 12: Constraining the Core

Virtex-5 Devices

Figure 6-6, page 75 illustrates the TBI input logic provided by the example design for the Virtex-5 family. IODELAY elements are instantiated on the TBI data input path as illustrated: the number of tap delays is currently set to zero. This can be modified in the UCF file, if desired, to de-skew the bus for PCB routing. A fixed tap delay is applied to delay the pma_rx_clk0 clock so that it correctly samples the TBI data at the IOB IDDR register, thereby meeting TBI setup and hold timing.

The tap delays are applied using the following UCF syntax.

#-----------------------------------------------------------

# To Adjust TBI Rx Input Setup/Hold Timing

#-----------------------------------------------------------

INST "core_wrapper/delay_pma_rx_clk" IDELAY_VALUE = "63";

INST "core_wrapper/tbi_rx_data_bus[9].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[8].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[7].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[6].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[5].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[4].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[3].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[2].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[1].delay_tbi_rx_data" IDELAY_VALUE = "0";

INST "core_wrapper/tbi_rx_data_bus[0].delay_tbi_rx_data" IDELAY_VALUE = "0";

The value of IDELAY_VALUE for the pma_rx_clk0 clock is preconfigured in the example designs to meet the setup and hold constraints for the example TBI pinout in the particular device. The setup/hold timing which is achieved after place-and-route is reported in the datasheet section of the TRCE report (created by the implement script). See “Understanding Timing Reports for Setup/Hold Timing.”

Constraints When Implementing an External GMII

The constraints defined in this section are implemented in the UCF for the example designs delivered with the core. Sections from this UCF have been copied into the following examples, and should be studied in conjunction with the HDL source code for the example design. See also the section, “Implementing External GMII,” page 61.

Clock Period Constraints

When implementing an external GMII, the Transmitter Elastic Buffer delivered with the example design (or similar logic) must be used. The input transmitter GMII signals are then synchronous to their own clock domain (gmii_tx_clk is used in the example design). This clock must be constrained for a clock frequency of 125 MHz. The following UCF syntax shows the necessary constraints being applied to the example design.

172	www.xilinx.com	Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
		UG155 March 24, 2008