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Xilinx 1000BASE-X manual Configuration and Status, 14Control Register Register

Models: 1000BASE-X

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Chapter 9: Configuration and Status

Register 0: Control Register

MDIO Register 0: Control Register

15		14	13	12	11	10	9	8	7	6	5	4	0

Reg 0

	RESET	LOOPBACK	SPEED	AUTO-NEG ENABLE	POWER DOWN	ISOLATE	RESTART AUTO-NEG	DUPLEX MODE	COLLISION TEST	SPEED	UNIDIRECTIONAL ENABLE		RESERVED

Table 9-14:Control Register (Register 0)

Bit(s)	Name		Description	Attributes	Default
Bit(s)	Name		Description	Attributes	Value
					Value

0.15	Reset	1	= PCS/PMA reset	read/write	0
		0	= Normal Operation	self clearing

0.14	Loopback	1	= Enable Loopback Mode	read/write	0
		0	= Disable Loopback Mode
		When used with a RocketIO transceiver,
		the core is placed in internal loopback
		mode.
		With the TBI version, Bit 1 is connected to
		ewrap. When set to ‘1’ indicates to the
		external PMA module to enter loopback
		mode.
		See “Loopback,” page 197.

0.13	Speed	Always returns a 0 for this bit. Together		returns 0	0
	Selection	with bit 0.6, speed selection of 1000 Mbps
	(LSB)	is identified.

0.12	Auto-	Ignore this bit because Auto-Negotiation		read/ write	1
	Negotiation	is not included.
	Enable

0.11	Power Down	1	= Power down	read/ write	0
		0	= Normal operation
		With the PMA option, when set to ’1’ the
		RocketIO transceiver is placed in a low-
		power state. This bit requires a reset (see
		bit 0.15) to clear.
		With the TBI version this register bit has
		no effect.

0.10	Isolate	1	= Electrically Isolate PHY from GMII	read/write	1
		0	= Normal operation

130	www.xilinx.com	Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
		UG155 March 24, 2008

Image 130

Xilinx 1000BASE-X manual Configuration and Status, 14Control Register Register

Contents

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or Sgmii UG155 March 24Revision History Date Doc Revision VersionTable of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 1Functional Block Diagram Using RocketIO Transceiver Schedule of FiguresAuto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 5Optional Auto-Negotiation Interface Signal Pinout Schedule of Tables33SGMII Auto-Negotiation Advertisement Register 4 Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleOnline Document Conventions Meaning or Use ExamplePreface About This Guide About the Core Designs Using RocketIO TransceiversIntroduction Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support Ethernet 1000BASE-X PCS/PMA or Sgmii CoreDocument FeedbackIntroduction Core Architecture System OverviewPCS Receive Engine and Synchronization Gmii BlockPCS Transmit Engine Optional Auto-Negotiation BlockRocketIO Interface Block Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceOptional PCS Management Registers System Overview8B/10B Decoder Core Interfaces8B/10B Encoder Receiver Elastic BufferCore Interfaces Core Architecture Core Interfaces Core Architecture Client Side Interface Gmii PinoutEthernet 1000BASE-X PCS/PMA or Sgmii Common Signal Pinout 2Other Common Signals Direction DescriptionMdio Management Interface Pinout Optional MACAuto-Negotiation Signal Pinout Configuration Vector Optional5Optional Auto-Negotiation Interface Signal Pinout Dynamic Switching Signal Pinout Physical Side InterfaceEthernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout GUI Interface Generating and Customizing the CoreComponent Name Core Functionality Select StandardGenerating and Customizing the Core Mdio Management Interface SGMII/Dynamic Standard Switching Elastic Buffer OptionsPhysical Interface Auto-Negotiation3SGMII/Dynamic Standard Switching Options Screen Parameter Values in the XCO File RocketIO Tile ConfigurationParameter Values in the XCO File Output Generation TBIDesigning with the Core Design OverviewDesigning with the Core 1000BASE-X Standard with TBI Example Design Design OverviewSgmii Standard Using a RocketIO Transceiver Example Design Example Design Performing the Sgmii StandardSgmii Standard with TBI Transceiver Example Design 4Example Design Performing the Sgmii StandardGenerate the Core Design GuidelinesExamine the Example Design Provided with the Core Create a Bitstream Write an HDL ApplicationSynthesize your Design Simulate and Download your DesignUse Supported Design Flows Recognize Timing Critical SignalsKeep it Registered Make Only Allowed ModificationsGmii Transmission Using the Client-side Gmii Data PathNormal Frame Transmission Gmii Reception Error PropagationUsing the Client-side Gmii Data Path Normal Frame ReceptionFrame Reception with Errors Normal Frame Reception with Extension FieldBit0 Link Status Statusvector40 signalsFalse Carrier Bit1 Link SynchronizationBits42 Code Group Reception Indicators Gmii TransmissionGmii Reception Gigabit per Second Frame Transmission Designing with Client-side Gmii for the Sgmii StandardOverview Megabit per Second Frame TransmissionGigabit per Second Frame Reception Megabit per Second Frame ReceptionImplementing External Gmii Using the Gmii as an Internal ConnectionUsing the Gmii as an Internal Connection Gmii Transmitter LogicVirtex-II Pro and Virtex-II Devices 14GMII Transmitter LogicSpartan-3, Spartan-3E and Spartan-3A Devices Implementing External GmiiVirtex-4 Devices 16External Gmii Transmitter Logic for Virtex-4 DevicesVirtex-5 Devices 17External Gmii Transmitter Logic for Virtex-5 DevicesGmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Ten-Bit-Interface Logic Ten-Bit InterfaceTransmitter Logic Virtex-II and Virtex-II Pro Devices Receiver LogicTen-Bit Interface Ten-Bit-Interface Logic 2Ten-Bit-Interface Receiver LogicComponentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBITen-Bit Interface RocketIO Transceiver Logic 1000BASE-X with RocketIO TransceiversVirtex-II Pro Devices 1000BASE-X with RocketIO Transceivers 11000BASE-X Connection to a Virtex-II Pro MGTVirtex-4 FX Devices RocketIO Transceiver Logic21000BASE-X Connection to Virtex-4 MGT Virtex-5 LXT and SXT Devices Virtex-5 RocketIO GTP Wizard31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 FXT Devices Virtex-5 RocketIO GTX Wizard41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIOVirtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Receiver Elastic Buffer Implementations Selecting the Buffer Implementation from the GUIRequirement for the Fpga Fabric Rx Elastic Buffer AnalysisRocketIO Rx Elastic Buffer Receiver Elastic Buffer ImplementationsRocketIO Logic using the RocketIO Rx Elastic Buffer Closely Related Clock SourcesRocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Mdio Management Interface Configuration and StatusMdio Bus System Mdio Transactions Configuration and Status1Abbreviations and Terms Read Transaction Mdio AddressingWrite Transaction Mdio Management Interface 1Abbreviations and TermsConnecting the Mdio to an Internally Integrated STA Connecting the Mdio to an External STAManagement Registers 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers 2MDIO Registers for 1000BASE-X with Auto-NegotiationMdio Register 0 Control Register Register 0 Control Register3Control Register Register Management Registers 3Control Register Register LSBMdio Register 1 Status Register Register 1 Status Register4Status Register Register Management Registers 4Status Register Register Registers 2 and 3 PHY IdentifiersRegisters 2 and 3 PHY Identifiers Mdio Register 4 Auto-Negotiation Advertisement Configuration and Status 5PHY Identifier Registers 2Register 4 Auto-Negotiation Advertisement Auto-Negotiation Advertisement Register RegisterRegister 5 Auto-Negotiation Link Partner Base Mdio Register 5 Auto-Negotiation Link Partner BaseMdio Register 6 Auto-Negotiation Expansion Register 6 Auto-Negotiation ExpansionRegister 7 Next Page Transmit 8Auto-Negotiation Expansion Register RegisterMdio Register 8 Next Page Receive Register 8 Next Page Receive10Auto-Negotiation Next Page Receive Register Mdio Register 15 Extended Status Register Register 15 Extended Status11Extended Status Register Register 1000BASE-X Standard Without the Optional Auto-Negotiation 13MDIO Registers for 1000BASE-X without Auto-Negotiation14Control Register Register Management Registers 14Control Register Register 15Status Register RegisterConfiguration and Status 15Status Register Register 16PHY Identifier Registers 2 Registers 2 and 3 Phy IdentifierMdio Registers 2 and 3 PHY Identifier Mdio Register 15 Extended StatusConfiguration and Status 17Extended Status Register 18MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard Using the Optional Auto-NegotiationRegister 0 Sgmii Control Mdio Register 0 Sgmii ControlConfiguration and Status 19SGMII Control Register Mdio Register 1 Sgmii Status Register 1 Sgmii StatusManagement Registers 19SGMII Control Register 20SGMII Status RegisterConfiguration and Status 20SGMII Status Register Mdio Register 4 Sgmii Auto-Negotiation Advertisement Register 4 Sgmii Auto-Negotiation Advertisement21PHY Identifier Registers 2 22SGMII Auto-Negotiation Advertisement RegisterRegister 5 Sgmii Auto-Negotiation Link Partner Ability Mdio Register 5 Sgmii Auto-Negotiation Link Partner AbilityRegister 6 Sgmii Auto-Negotiation Expansion Register 7 Sgmii Auto-Negotiation Next Page TransmitMdio Register 8 Sgmii Next Page Receive Register 8 Sgmii Next Page Receive26SGMII Auto-Negotiation Next Page Receive Register Mdio Register 15 Sgmii Extended Status Register 15 Sgmii Extended Status27SGMII Extended Status Register Register Mdio Register 16 Sgmii Auto-Negotiation Interrupt Control Register 16 Sgmii Auto-Negotiation Interrupt Control28SGMII Auto-Negotiation Interrupt Control Register Sgmii Standard without the Optional Auto-Negotiation 29MDIO Registers for 1000BASE-X with Auto-NegotiationConfiguration and Status 30SGMII Control Register Management Registers 30SGMII Control Register 31SGMII Status RegisterConfiguration and Status 31SGMII Status Register 32PHY Identifier Registers 2 33SGMII Auto-Negotiation Advertisement RegisterBoth 1000BASE-X and Sgmii Standards 34SGMII Extended Status Register RegisterOptional Configuration Vector Optional Configuration VectorRegister 17 Vendor-specific Standard Selection Register 36Optional Configuration and Status Vectors Signal Direction Clock Description DomainAuto-Negotiation Overview of OperationAuto-Negotiation Overview of Operation Sgmii StandardSgmii Auto-Negotiation 1000BASE-X Standard Setting the Configurable Link TimerUsing the Auto-Negotiation Interrupt Simulating Auto-NegotiationDynamic Switching of 1000BASE-X and Sgmii Standards Typical ApplicationSetting the Auto-Negotiation Link Timer Selecting the Power-On / Reset StandardSwitching the Standard Using Mdio Operation of the CoreOperation of the Core 160 Constraining the Core Required ConstraintsClock Period Constraints Setting MGT AttributesMGT Transceiver Placement Constraints Constraining the CoreRequired Constraints # EnmcommaalignVirtex-4 RocketIO MGTs for 1000BASE-X Constraints 1Local Clock Place and Route for Top MGTSetting MGT Transceiver Attributes MGT Placement ConstraintsSetting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Setting GTX Transceiver Attributes Ten-Bit Interface ConstraintsTen-Bit Interface IOB Constraints TBI Input Setup/Hold Timing 1Input TBI Timing Symbol Min Max UnitsVirtex-4 Devices Constraints When Implementing an External Gmii Virtex-5 DevicesGmii IOB Constraints Gmii Input Setup/Hold Timing 2Input Gmii Timing Symbol Min Max UnitsEthernet 1000BASE-X PCS/PMA or Sgmii 175 Devices Other Than Virtex-4 or Virtex-5 Understanding Timing Reports for Setup/Hold TimingVirtex-4 or Virtex-5 Devices 4Timing Report Setup/Hold Illustration 178 Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC CoreInterfacing to Other Cores MACVirtex-II Pro Devices Integrating with the 1-Gigabit Ethernet MAC Core182 Virtex-5 LXT and SXT Devices GTPVirtex-5 FXT Devices ClkdvIntegrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Startup Sequencing Power ManagementSpecial Design Considerations LoopbackCore with RocketIO Transceiver Special Design ConsiderationsLoopback 200 Pre-implementation Simulation Using the Simulation ModelImplementing the Design SynthesisGenerating the Xilinx Netlist ImplementationXST Verilog Mapping the DesignStatic Timing Analysis Using the ModelPost-Implementation Simulation Generating a BitstreamOther Implementation Information Virtex-5 DevicesSimulation Core Verification, Compliance, and InteroperabilityVerification Hardware Verification206 Latency for 1000BASE-X PCS with TBI Core LatencyCore Latency Transmit Path LatencyLatency for Sgmii Requirement for DCM Phase Shifting Calculating the DCM Fixed Phase Shift ValueFinding the Ideal Phase Shift Value for Your System Appendix C Calculating the DCM Fixed Phase Shift Value 1000BASE-X State Machines IntroductionEven Transmission Case Start of Frame EncodingAppendix D 1000BASE-X State Machines Odd Transmission Case Reception of the Even CaseStart of Frame Encoding Reception of the Odd Case Preamble Shrinkage End of Frame EncodingEnd of Frame Encoding 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 Rx Elastic Buffers Depths and Maximum Frame Sizes Rx Elastic Buffer SpecificationsRocketIO Rx Elastic Buffers Appendix E Rx Elastic Buffer Specifications Virtex-II Pro and Virtex-5 DevicesVirtex-4 FX Rx Elastic Buffers Depths and Maximum Frame SizesSgmii Fabric Rx Elastic Buffer Figure E-2Elastic Buffer Size for all RocketIO familiesTBI Rx Elastic Buffer For Sgmii / Dynamic SwitchingFor 1000BASE-X Clock Correction Idle Character Removal at 1Gbps 1000BASE-X and SgmiiIdle Character Removal at 10 Mbps Sgmii Idle Character Removal at 100 Mbps SgmiiClock Correction Jumbo Frame Reception Maximum Frame Sizes for Sustained Frame ReceptionRocketIO Sgmii Fabric Buffer Debugging Guide Problems with the MdioProblems with Data Reception or Transmission General ChecksProblems in Obtaining a Link Auto-Negotiation Disabled Problems with Auto-NegotiationAppendix F Debugging Guide Problems with a High Bit Error Rate Problems with a High Bit Error RateSymptoms DebuggingRocketIO Transceiver Specific Checks