
R
Chapter 9: Configuration and Status
Register 0: Control Register
MDIO Register 0: Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 0 | |
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Reg 0 |
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| RESET | LOOPBACK | SPEED | POWER DOWN | ISOLATE | RESTART | DUPLEX MODE | COLLISION TEST | SPEED | UNIDIRECTIONAL ENABLE |
| RESERVED |
Table 9-14: Control Register (Register 0)
Bit(s) | Name |
| Description | Attributes | Default |
| Value | ||||
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0.15 | Reset | 1 | = PCS/PMA reset | read/write | 0 |
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| 0 | = Normal Operation | self clearing |
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0.14 | Loopback | 1 | = Enable Loopback Mode | read/write | 0 |
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| 0 | = Disable Loopback Mode |
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| When used with a RocketIO transceiver, |
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| the core is placed in internal loopback |
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| mode. |
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| With the TBI version, Bit 1 is connected to |
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| ewrap. When set to ‘1’ indicates to the |
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| external PMA module to enter loopback |
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| mode. |
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| See “Loopback,” page 197. |
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0.13 | Speed | Always returns a 0 for this bit. Together | returns 0 | 0 | |
| Selection | with bit 0.6, speed selection of 1000 Mbps |
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| (LSB) | is identified. |
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0.12 | Auto- | Ignore this bit because | read/ write | 1 | |
| Negotiation | is not included. |
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| Enable |
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0.11 | Power Down | 1 | = Power down | read/ write | 0 |
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| 0 | = Normal operation |
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| With the PMA option, when set to ’1’ the |
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| RocketIO transceiver is placed in a low- |
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| power state. This bit requires a reset (see |
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| bit 0.15) to clear. |
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| With the TBI version this register bit has |
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| no effect. |
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0.10 | Isolate | 1 | = Electrically Isolate PHY from GMII | read/write | 1 |
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| 0 | = Normal operation |
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130 | www.xilinx.com | Ethernet |
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| UG155 March 24, 2008 |