Receiver Elastic Buffer Implementations
R
Considering the 10 Mbps case, we would need 152200/5000 = 31 FIFO entries in the Elastic Buffer above and below the half way point to guarantee that the buffer will not under or overflow during frame reception. This assumes that frame reception begins when the buffer is exactly half full.
The size of the Rx Elastic Buffer in the RocketIOs is 64 entries. However, we cannot assume that the buffer is exactly half full at the start of frame reception. Additionally, the underflow and overflow thresholds are not exact (see Appendix E, “Rx Elastic Buffer Specifications” for more information).
To guarantee reliable SGMII operation at 10 Mbps
Appendix E, “Rx Elastic Buffer Specifications” provides further information about all Rx Elastic Buffers used by the core. Information about the reception of jumbo frames is also provided.
The RocketIO Rx Elastic Buffer
The Elastic Buffer in the RocketIO can be used reliably when the following conditions are met:
•10 Mbps operation is not required (for example, when connecting the core to the Xilinx
•When the clocks are closely related (see the following section).
If there is any doubt, select the FPGA fabric Rx Elastic Buffer Implementation.
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