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Xilinx 1000BASE-X manual Mdio Register 1 Status Register, 4Status Register Register

Models: 1000BASE-X

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Chapter 9: Configuration and Status

Register 1: Status Register

MDIO Register 1: Status Register

15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Reg 1

	100BASE-T4	100BASE-X FULL DUPLEX	100BASE-X HALF DUPLEX	10Mb/s FULL DUPLEX	10Mb/s HALF DUPLEX	100BASE-T2 FULL DUPLEX	100BASE-T2 HALF DUPLEX	EXTENDED STATUS	UNIDIRECTIONAL ANILITY	MF PREAMBLE SUPPRESSION	AUTO-NEG COMPLETE	REMOTE FAULT	AUTO-NEG ABILITY	LINK STATUS	JABBER DETECT	EXTENDED CAPABILITY

Table 9-4:Status Register (Register 1)

	Bit(s)	Name	Description	Attributes	Default
	Bit(s)	Name	Description	Attributes	Value
					Value

	1.15	100BASE-T4	Always returns a ‘0’ as 100BASE-T4 is not	Returns 0	0
			supported.

	1.14	100BASE-X Full	Always returns a ‘0’ as 100BASE-X full	Returns 0	0
		Duplex	duplex is not supported.

	1.13	100BASE-X Half	Always returns a ‘0’ as 100BASE-X half	Returns 0	0
		Duplex	duplex is not supported.

	1.12	10 Mbps Full Duplex	Always returns a ‘0’ as 10 Mbps full	Returns 0	0
			duplex is not supported.

	1.11	10 Mbps Half Duplex	Always returns a ‘0’ as 10 Mbps half	Returns 0	0
			duplex is not supported

	1.10	100BASE-T2 Full	Always returns a ‘0’ as 100BASE-T2 full	Returns 0	0
		Duplex	duplex is not supported.

	1.9	100BASE-T2 Half	Always returns a ‘0’ as 100BASE-T2 Half	Returns 0	0
		Duplex	Duplex is not supported.

	1.8	Extended Status	Always returns a ‘1’ to indicate the	Returns 1	1
			presence of the Extended Register
			(Register 15).

	1.7	Unidirectional	Always returns a ‘1,’ writes ignored	Returns 1	1
		Ability

	1.6	MF Preamble	Always returns a ‘1’ to indicate that	Returns 1	1
		Suppression	Management Frame Preamble
			Suppression is supported.

	1.5	Auto- Negotiation	1 = Auto-Negotiation process completed	Read only	0
		Complete	0 = Auto-Negotiation process not
			0 = Auto-Negotiation process not
			completed

122	www.xilinx.com	Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
		UG155 March 24, 2008

Image 122

Xilinx 1000BASE-X manual Mdio Register 1 Status Register, 4Status Register Register

Contents

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or Sgmii UG155 March 24Revision History Date Doc Revision VersionTable of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 1Functional Block Diagram Using RocketIO Transceiver Schedule of FiguresAuto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 5Optional Auto-Negotiation Interface Signal Pinout Schedule of Tables33SGMII Auto-Negotiation Advertisement Register 4 Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleOnline Document Conventions Meaning or Use ExamplePreface About This Guide About the Core Designs Using RocketIO TransceiversIntroduction Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support Ethernet 1000BASE-X PCS/PMA or Sgmii CoreDocument FeedbackIntroduction Core Architecture System OverviewPCS Receive Engine and Synchronization Gmii BlockPCS Transmit Engine Optional Auto-Negotiation BlockRocketIO Interface Block Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceOptional PCS Management Registers System Overview8B/10B Decoder Core Interfaces8B/10B Encoder Receiver Elastic BufferCore Interfaces Core Architecture Core Interfaces Core Architecture Client Side Interface Gmii PinoutEthernet 1000BASE-X PCS/PMA or Sgmii Common Signal Pinout 2Other Common Signals Direction DescriptionMdio Management Interface Pinout Optional MAC5Optional Auto-Negotiation Interface Signal Pinout Configuration Vector OptionalAuto-Negotiation Signal Pinout Dynamic Switching Signal Pinout Physical Side InterfaceEthernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Component Name Generating and Customizing the CoreGUI Interface Generating and Customizing the Core Select StandardCore Functionality Mdio Management Interface SGMII/Dynamic Standard Switching Elastic Buffer OptionsPhysical Interface Auto-Negotiation3SGMII/Dynamic Standard Switching Options Screen Parameter Values in the XCO File RocketIO Tile ConfigurationParameter Values in the XCO File Output Generation TBIDesigning with the Core Design OverviewDesigning with the Core 1000BASE-X Standard with TBI Example Design Design OverviewSgmii Standard Using a RocketIO Transceiver Example Design Example Design Performing the Sgmii StandardSgmii Standard with TBI Transceiver Example Design 4Example Design Performing the Sgmii StandardExamine the Example Design Provided with the Core Design GuidelinesGenerate the Core Create a Bitstream Write an HDL ApplicationSynthesize your Design Simulate and Download your DesignUse Supported Design Flows Recognize Timing Critical SignalsKeep it Registered Make Only Allowed ModificationsNormal Frame Transmission Using the Client-side Gmii Data PathGmii Transmission Gmii Reception Error PropagationUsing the Client-side Gmii Data Path Normal Frame ReceptionFrame Reception with Errors Normal Frame Reception with Extension FieldBit0 Link Status Statusvector40 signalsFalse Carrier Bit1 Link SynchronizationBits42 Code Group Reception Indicators Gmii TransmissionGmii Reception Gigabit per Second Frame Transmission Designing with Client-side Gmii for the Sgmii StandardOverview Megabit per Second Frame TransmissionGigabit per Second Frame Reception Megabit per Second Frame ReceptionImplementing External Gmii Using the Gmii as an Internal ConnectionUsing the Gmii as an Internal Connection Gmii Transmitter LogicVirtex-II Pro and Virtex-II Devices 14GMII Transmitter LogicSpartan-3, Spartan-3E and Spartan-3A Devices Implementing External GmiiVirtex-4 Devices 16External Gmii Transmitter Logic for Virtex-4 DevicesVirtex-5 Devices 17External Gmii Transmitter Logic for Virtex-5 DevicesGmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Transmitter Logic Ten-Bit InterfaceTen-Bit-Interface Logic Ten-Bit Interface Receiver LogicVirtex-II and Virtex-II Pro Devices Ten-Bit-Interface Logic 2Ten-Bit-Interface Receiver LogicComponentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBITen-Bit Interface Virtex-II Pro Devices 1000BASE-X with RocketIO TransceiversRocketIO Transceiver Logic 1000BASE-X with RocketIO Transceivers 11000BASE-X Connection to a Virtex-II Pro MGTVirtex-4 FX Devices RocketIO Transceiver Logic21000BASE-X Connection to Virtex-4 MGT Virtex-5 LXT and SXT Devices Virtex-5 RocketIO GTP Wizard31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 FXT Devices Virtex-5 RocketIO GTX Wizard41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIOVirtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Receiver Elastic Buffer Implementations Selecting the Buffer Implementation from the GUIRequirement for the Fpga Fabric Rx Elastic Buffer AnalysisRocketIO Rx Elastic Buffer Receiver Elastic Buffer ImplementationsRocketIO Logic using the RocketIO Rx Elastic Buffer Closely Related Clock SourcesRocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Mdio Bus System Configuration and StatusMdio Management Interface 1Abbreviations and Terms Configuration and StatusMdio Transactions Read Transaction Mdio AddressingWrite Transaction Mdio Management Interface 1Abbreviations and TermsConnecting the Mdio to an Internally Integrated STA Connecting the Mdio to an External STAManagement Registers 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers 2MDIO Registers for 1000BASE-X with Auto-Negotiation3Control Register Register Register 0 Control RegisterMdio Register 0 Control Register Management Registers 3Control Register Register LSB4Status Register Register Register 1 Status RegisterMdio Register 1 Status Register Registers 2 and 3 PHY Identifiers Registers 2 and 3 PHY IdentifiersManagement Registers 4Status Register Register Mdio Register 4 Auto-Negotiation Advertisement Configuration and Status 5PHY Identifier Registers 2Register 4 Auto-Negotiation Advertisement Auto-Negotiation Advertisement Register RegisterRegister 5 Auto-Negotiation Link Partner Base Mdio Register 5 Auto-Negotiation Link Partner BaseMdio Register 6 Auto-Negotiation Expansion Register 6 Auto-Negotiation ExpansionRegister 7 Next Page Transmit 8Auto-Negotiation Expansion Register Register10Auto-Negotiation Next Page Receive Register Register 8 Next Page ReceiveMdio Register 8 Next Page Receive 11Extended Status Register Register Register 15 Extended StatusMdio Register 15 Extended Status Register 1000BASE-X Standard Without the Optional Auto-Negotiation 13MDIO Registers for 1000BASE-X without Auto-Negotiation14Control Register Register Management Registers 14Control Register Register 15Status Register RegisterConfiguration and Status 15Status Register Register 16PHY Identifier Registers 2 Registers 2 and 3 Phy IdentifierMdio Registers 2 and 3 PHY Identifier Mdio Register 15 Extended StatusConfiguration and Status 17Extended Status Register 18MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard Using the Optional Auto-NegotiationRegister 0 Sgmii Control Mdio Register 0 Sgmii ControlConfiguration and Status 19SGMII Control Register Mdio Register 1 Sgmii Status Register 1 Sgmii StatusManagement Registers 19SGMII Control Register 20SGMII Status RegisterConfiguration and Status 20SGMII Status Register Mdio Register 4 Sgmii Auto-Negotiation Advertisement Register 4 Sgmii Auto-Negotiation Advertisement21PHY Identifier Registers 2 22SGMII Auto-Negotiation Advertisement RegisterRegister 5 Sgmii Auto-Negotiation Link Partner Ability Mdio Register 5 Sgmii Auto-Negotiation Link Partner AbilityRegister 6 Sgmii Auto-Negotiation Expansion Register 7 Sgmii Auto-Negotiation Next Page Transmit26SGMII Auto-Negotiation Next Page Receive Register Register 8 Sgmii Next Page ReceiveMdio Register 8 Sgmii Next Page Receive 27SGMII Extended Status Register Register Register 15 Sgmii Extended StatusMdio Register 15 Sgmii Extended Status 28SGMII Auto-Negotiation Interrupt Control Register Register 16 Sgmii Auto-Negotiation Interrupt ControlMdio Register 16 Sgmii Auto-Negotiation Interrupt Control Sgmii Standard without the Optional Auto-Negotiation 29MDIO Registers for 1000BASE-X with Auto-NegotiationConfiguration and Status 30SGMII Control Register Management Registers 30SGMII Control Register 31SGMII Status RegisterConfiguration and Status 31SGMII Status Register 32PHY Identifier Registers 2 33SGMII Auto-Negotiation Advertisement RegisterBoth 1000BASE-X and Sgmii Standards 34SGMII Extended Status Register RegisterRegister 17 Vendor-specific Standard Selection Register Optional Configuration VectorOptional Configuration Vector 36Optional Configuration and Status Vectors Signal Direction Clock Description DomainAuto-Negotiation Overview of OperationAuto-Negotiation Sgmii Auto-Negotiation Sgmii StandardOverview of Operation 1000BASE-X Standard Setting the Configurable Link TimerUsing the Auto-Negotiation Interrupt Simulating Auto-NegotiationDynamic Switching of 1000BASE-X and Sgmii Standards Typical ApplicationSetting the Auto-Negotiation Link Timer Selecting the Power-On / Reset StandardSwitching the Standard Using Mdio Operation of the CoreOperation of the Core 160 Constraining the Core Required ConstraintsClock Period Constraints Setting MGT AttributesMGT Transceiver Placement Constraints Constraining the CoreRequired Constraints # EnmcommaalignVirtex-4 RocketIO MGTs for 1000BASE-X Constraints 1Local Clock Place and Route for Top MGTSetting MGT Transceiver Attributes MGT Placement ConstraintsSetting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Setting GTX Transceiver Attributes Ten-Bit Interface ConstraintsTen-Bit Interface IOB Constraints TBI Input Setup/Hold Timing 1Input TBI Timing Symbol Min Max UnitsVirtex-4 Devices Constraints When Implementing an External Gmii Virtex-5 DevicesGmii IOB Constraints Gmii Input Setup/Hold Timing 2Input Gmii Timing Symbol Min Max UnitsEthernet 1000BASE-X PCS/PMA or Sgmii 175 Virtex-4 or Virtex-5 Devices Understanding Timing Reports for Setup/Hold TimingDevices Other Than Virtex-4 or Virtex-5 4Timing Report Setup/Hold Illustration 178 Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC CoreInterfacing to Other Cores MACVirtex-II Pro Devices Integrating with the 1-Gigabit Ethernet MAC Core182 Virtex-5 LXT and SXT Devices GTPVirtex-5 FXT Devices ClkdvIntegrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Startup Sequencing Power ManagementSpecial Design Considerations LoopbackCore with RocketIO Transceiver Special Design ConsiderationsLoopback 200 Pre-implementation Simulation Using the Simulation ModelImplementing the Design SynthesisGenerating the Xilinx Netlist ImplementationXST Verilog Mapping the DesignStatic Timing Analysis Using the ModelPost-Implementation Simulation Generating a BitstreamOther Implementation Information Virtex-5 DevicesSimulation Core Verification, Compliance, and InteroperabilityVerification Hardware Verification206 Latency for 1000BASE-X PCS with TBI Core LatencyCore Latency Transmit Path LatencyLatency for Sgmii Finding the Ideal Phase Shift Value for Your System Calculating the DCM Fixed Phase Shift ValueRequirement for DCM Phase Shifting Appendix C Calculating the DCM Fixed Phase Shift Value 1000BASE-X State Machines IntroductionAppendix D 1000BASE-X State Machines Start of Frame EncodingEven Transmission Case Start of Frame Encoding Reception of the Even CaseOdd Transmission Case Reception of the Odd Case End of Frame Encoding End of Frame EncodingPreamble Shrinkage 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 RocketIO Rx Elastic Buffers Rx Elastic Buffer SpecificationsRx Elastic Buffers Depths and Maximum Frame Sizes Appendix E Rx Elastic Buffer Specifications Virtex-II Pro and Virtex-5 DevicesVirtex-4 FX Rx Elastic Buffers Depths and Maximum Frame SizesSgmii Fabric Rx Elastic Buffer Figure E-2Elastic Buffer Size for all RocketIO familiesFor 1000BASE-X For Sgmii / Dynamic SwitchingTBI Rx Elastic Buffer Clock Correction Idle Character Removal at 1Gbps 1000BASE-X and SgmiiClock Correction Idle Character Removal at 100 Mbps SgmiiIdle Character Removal at 10 Mbps Sgmii RocketIO Sgmii Fabric Buffer Maximum Frame Sizes for Sustained Frame ReceptionJumbo Frame Reception Debugging Guide Problems with the MdioProblems with Data Reception or Transmission General ChecksAppendix F Debugging Guide Problems with Auto-NegotiationProblems in Obtaining a Link Auto-Negotiation Disabled Problems with a High Bit Error Rate Problems with a High Bit Error RateSymptoms DebuggingRocketIO Transceiver Specific Checks