Registers 2 and 3 PHY Identifiers | Xilinx 1000BASE-X specs

Management Registers

Table 9-4:Status Register (Register 1) (Continued)

R

	Bit(s)	Name	Description	Attributes	Default
	Bit(s)	Name	Description	Attributes	Value
					Value

	1.4	Remote Fault	1 = Remote fault condition detected	Read only	0
			0 = No remote fault condition detected	Self-
				clearing
				on read

	1.3	Auto- Negotiation	Always returns a ‘1’ for this bit to indicate	Returns 1	1
		Ability	that the PHY is capable of Auto-
			Negotiation.

	1.2	Link Status1	1 = Link is up	Read only	0
			0 = Link is down	Self
			Latches '0' if Link Status goes down.	clearing
			Latches '0' if Link Status goes down.	on read
			Clears to current Link Status on read.	on read
			Clears to current Link Status on read.
			See table note for Link Status behavior.

	1.1	Jabber Detect	Always returns a ‘0’ for this bit since	Returns 0	0
			Jabber Detect is not supported.

	1.0	Extended Capability	Always returns a ‘0’ for this bit since no	Returns 0	0
			extended register set is supported.

1.When high, the link is valid: synchronization of the link has been obtained and Auto-Negotiation (if present and enabled) has completed.

When low, a valid link has not been established. Either link synchronization has failed or Auto-Negotiation (if present and enabled) has failed to complete.

Regardless of whether Auto-Negotiation is enabled or disabled, there can be some delay to the deassertion of this signal following the loss of synchronization of a previously successful link. This is due to the Auto-Negotiation state machine which requires that synchronization is lost for an entire link timer duration before changing state. For more information, see the 802.3 specification.

Registers 2 and 3: PHY Identifiers

Registers 2 and 3: PHY Identifiers

15

Reg 2

15		10	9
Reg 3
Reg 3

	UNIQUE ID	ORGANIZE

ORGANIZE

UNIQUE ID

MAUFACTURER

MODEL NO

0

4	3	0
		REVISION NO

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

www.xilinx.com

123

UG155 March 24, 2008

Image 123

Xilinx 1000BASE-X manual Registers 2 and 3 PHY Identifiers, Management Registers 4Status Register Register

Contents

UG155 March 24 LogiCORE IP Ethernet 1000BASE-X PCS/PMA or Sgmii Date Doc Revision Version Revision History Table of Contents Using the Client-side Gmii Data Path Configuration and Status Interfacing to Other Cores Appendix C Calculating the DCM Fixed Phase Shift Value UG155 March 24 Schedule of Figures 1Functional Block Diagram Using RocketIO Transceiver Auto-Negotiation Typical Application for Dynamic Switching 157 UG155 March 24 Schedule of Tables 5Optional Auto-Negotiation Interface Signal Pinout 33SGMII Auto-Negotiation Advertisement Register 4 About This Guide Guide Contents Convention Meaning or Use Example ConventionsTypographical Preface About This Guide Conventions Meaning or Use Example Online Document Preface About This Guide Recommended Design Experience Designs Using RocketIO TransceiversIntroduction About the Core Ethernet 1000BASE-X PCS/PMA or Sgmii Core Additional Core ResourcesTechnical Support Feedback Feedback Document Introduction System Overview Core Architecture Optional Auto-Negotiation Block Gmii BlockPCS Transmit Engine PCS Receive Engine and Synchronization System Overview Ethernet 1000BASE-X PCS/PMA or Sgmii with Ten-Bit-InterfaceOptional PCS Management Registers RocketIO Interface Block Receiver Elastic Buffer Core Interfaces8B/10B Encoder 8B/10B Decoder Core Interfaces Core Architecture Core Interfaces Core Architecture Gmii Pinout Client Side Interface Ethernet 1000BASE-X PCS/PMA or Sgmii 2Other Common Signals Direction Description Common Signal Pinout MAC Mdio Management Interface Pinout Optional Configuration Vector Optional Auto-Negotiation Signal Pinout5Optional Auto-Negotiation Interface Signal Pinout Physical Side Interface Dynamic Switching Signal Pinout Ethernet 1000BASE-X PCS/PMA or Sgmii 1000BASE-X PCS with TBI Pinout Generating and Customizing the Core GUI InterfaceComponent Name Select Standard Core FunctionalityGenerating and Customizing the Core Auto-Negotiation SGMII/Dynamic Standard Switching Elastic Buffer OptionsPhysical Interface Mdio Management Interface 3SGMII/Dynamic Standard Switching Options Screen RocketIO Tile Configuration Parameter Values in the XCO FileParameter Values in the XCO File TBI Output Generation Design Overview Designing with the Core Designing with the Core Design Overview 1000BASE-X Standard with TBI Example Design Example Design Performing the Sgmii Standard Sgmii Standard Using a RocketIO Transceiver Example Design 4Example Design Performing the Sgmii Standard Sgmii Standard with TBI Transceiver Example Design Design Guidelines Generate the CoreExamine the Example Design Provided with the Core Simulate and Download your Design Write an HDL ApplicationSynthesize your Design Create a Bitstream Make Only Allowed Modifications Recognize Timing Critical SignalsKeep it Registered Use Supported Design Flows Using the Client-side Gmii Data Path Gmii TransmissionNormal Frame Transmission Normal Frame Reception Error PropagationUsing the Client-side Gmii Data Path Gmii Reception Normal Frame Reception with Extension Field Frame Reception with Errors Bit1 Link Synchronization Statusvector40 signalsFalse Carrier Bit0 Link Status Gmii Transmission Bits42 Code Group Reception Indicators Gmii Reception Megabit per Second Frame Transmission Designing with Client-side Gmii for the Sgmii StandardOverview Gigabit per Second Frame Transmission Megabit per Second Frame Reception Gigabit per Second Frame Reception Gmii Transmitter Logic Using the Gmii as an Internal ConnectionUsing the Gmii as an Internal Connection Implementing External Gmii 14GMII Transmitter Logic Virtex-II Pro and Virtex-II Devices Implementing External Gmii Spartan-3, Spartan-3E and Spartan-3A Devices 16External Gmii Transmitter Logic for Virtex-4 Devices Virtex-4 Devices 17External Gmii Transmitter Logic for Virtex-5 Devices Virtex-5 Devices Gmii Receiver Logic 18External Gmii Receiver Logic Using the Client-side Gmii Data Path Ten-Bit Interface Ten-Bit-Interface LogicTransmitter Logic Receiver Logic Virtex-II and Virtex-II Pro DevicesTen-Bit Interface 2Ten-Bit-Interface Receiver Logic Ten-Bit-Interface Logic Componentnameblock Block Level from example design Method Idelay Iodelay IOB Logic Ibufg 7Alternate Ten-Bit Interface Receiver Logic Virtex-5 Devices Clock Sharing across Multiple Cores with TBI Clock Sharing across Multiple Cores with TBI Ten-Bit Interface 1000BASE-X with RocketIO Transceivers RocketIO Transceiver LogicVirtex-II Pro Devices 11000BASE-X Connection to a Virtex-II Pro MGT 1000BASE-X with RocketIO Transceivers RocketIO Transceiver Logic Virtex-4 FX Devices 21000BASE-X Connection to Virtex-4 MGT Virtex-5 RocketIO GTP Wizard Virtex-5 LXT and SXT Devices 31000BASE-X Connection to Virtex-5 GTP Transceivers Virtex-5 RocketIO GTX Wizard Virtex-5 FXT Devices 41000BASE-X Connection to Virtex-5 GTX Transceivers Clock Sharing Across Multiple Cores with RocketIO Clock Sharing Across Multiple Cores with RocketIO Virtex-4 FX Devices Componentname block Virtex-5 LXT and SXT Devices Ibufgds Virtex-5 FXT Devices DCM 1000BASE-X with RocketIO Transceivers Selecting the Buffer Implementation from the GUI Receiver Elastic Buffer Implementations Analysis Requirement for the Fpga Fabric Rx Elastic Buffer Receiver Elastic Buffer Implementations RocketIO Rx Elastic Buffer Closely Related Clock Sources RocketIO Logic using the RocketIO Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer RocketIO Logic with the Fabric Rx Elastic Buffer 3SGMII Connection to a Virtex-II Pro RocketIO Transceiver Virtex-4 Devices for Sgmii or Dynamic Standards Switching 4SGMII Connection to a Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or Sgmii 103 5SGMII Connection to a Virtex-5 RocketIO GTP Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 105 6SGMII Connection to a Virtex-5 RocketIO GTX Transceiver Ethernet 1000BASE-X PCS/PMA or Sgmii 107 108 Ethernet 1000BASE-X PCS/PMA or Sgmii 109 Sgmii Ethernet 1000BASE-X PCS/PMA or Sgmii 111 112 Ethernet 1000BASE-X PCS/PMA or Sgmii 113 114 Configuration and Status Mdio Management InterfaceMdio Bus System Configuration and Status Mdio Transactions1Abbreviations and Terms Mdio Management Interface 1Abbreviations and Terms Mdio AddressingWrite Transaction Read Transaction Connecting the Mdio to an External STA Connecting the Mdio to an Internally Integrated STA 2MDIO Registers for 1000BASE-X with Auto-Negotiation 1000BASE-X Standard Using the Optional Auto-NegotiationManagement Registers Management Registers Register 0 Control Register Mdio Register 0 Control Register3Control Register Register LSB Management Registers 3Control Register Register Register 1 Status Register Mdio Register 1 Status Register4Status Register Register Registers 2 and 3 PHY Identifiers Management Registers 4Status Register RegisterRegisters 2 and 3 PHY Identifiers Auto-Negotiation Advertisement Register Register Configuration and Status 5PHY Identifier Registers 2Register 4 Auto-Negotiation Advertisement Mdio Register 4 Auto-Negotiation Advertisement Mdio Register 5 Auto-Negotiation Link Partner Base Register 5 Auto-Negotiation Link Partner Base 8Auto-Negotiation Expansion Register Register Register 6 Auto-Negotiation ExpansionRegister 7 Next Page Transmit Mdio Register 6 Auto-Negotiation Expansion Register 8 Next Page Receive Mdio Register 8 Next Page Receive10Auto-Negotiation Next Page Receive Register Register 15 Extended Status Mdio Register 15 Extended Status Register11Extended Status Register Register 13MDIO Registers for 1000BASE-X without Auto-Negotiation 1000BASE-X Standard Without the Optional Auto-Negotiation 14Control Register Register 15Status Register Register Management Registers 14Control Register Register Configuration and Status 15Status Register Register Mdio Register 15 Extended Status Registers 2 and 3 Phy IdentifierMdio Registers 2 and 3 PHY Identifier 16PHY Identifier Registers 2 Configuration and Status 17Extended Status Register Mdio Register 0 Sgmii Control Sgmii Standard Using the Optional Auto-NegotiationRegister 0 Sgmii Control 18MDIO Registers for 1000BASE-X with Auto-Negotiation Configuration and Status 19SGMII Control Register 20SGMII Status Register Register 1 Sgmii StatusManagement Registers 19SGMII Control Register Mdio Register 1 Sgmii Status Configuration and Status 20SGMII Status Register 22SGMII Auto-Negotiation Advertisement Register Register 4 Sgmii Auto-Negotiation Advertisement21PHY Identifier Registers 2 Mdio Register 4 Sgmii Auto-Negotiation Advertisement Mdio Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 5 Sgmii Auto-Negotiation Link Partner Ability Register 7 Sgmii Auto-Negotiation Next Page Transmit Register 6 Sgmii Auto-Negotiation Expansion Register 8 Sgmii Next Page Receive Mdio Register 8 Sgmii Next Page Receive26SGMII Auto-Negotiation Next Page Receive Register Register 15 Sgmii Extended Status Mdio Register 15 Sgmii Extended Status27SGMII Extended Status Register Register Register 16 Sgmii Auto-Negotiation Interrupt Control Mdio Register 16 Sgmii Auto-Negotiation Interrupt Control28SGMII Auto-Negotiation Interrupt Control Register 29MDIO Registers for 1000BASE-X with Auto-Negotiation Sgmii Standard without the Optional Auto-Negotiation Configuration and Status 30SGMII Control Register 31SGMII Status Register Management Registers 30SGMII Control Register Configuration and Status 31SGMII Status Register 33SGMII Auto-Negotiation Advertisement Register 32PHY Identifier Registers 2 34SGMII Extended Status Register Register Both 1000BASE-X and Sgmii Standards Optional Configuration Vector Optional Configuration VectorRegister 17 Vendor-specific Standard Selection Register Signal Direction Clock Description Domain 36Optional Configuration and Status Vectors Overview of Operation Auto-Negotiation Auto-Negotiation Sgmii Standard Overview of OperationSgmii Auto-Negotiation Simulating Auto-Negotiation Setting the Configurable Link TimerUsing the Auto-Negotiation Interrupt 1000BASE-X Standard Typical Application Dynamic Switching of 1000BASE-X and Sgmii Standards Operation of the Core Selecting the Power-On / Reset StandardSwitching the Standard Using Mdio Setting the Auto-Negotiation Link Timer Operation of the Core 160 Required Constraints Constraining the Core Constraining the Core Setting MGT AttributesMGT Transceiver Placement Constraints Clock Period Constraints # Enmcommaalign Required Constraints 1Local Clock Place and Route for Top MGT Virtex-4 RocketIO MGTs for 1000BASE-X Constraints MGT Placement Constraints Setting MGT Transceiver Attributes Setting GTP Transceiver Attributes Ethernet 1000BASE-X PCS/PMA or Sgmii 167 UG155 March 24 Ten-Bit Interface Constraints Setting GTX Transceiver Attributes Ten-Bit Interface IOB Constraints 1Input TBI Timing Symbol Min Max Units TBI Input Setup/Hold Timing Virtex-4 Devices Virtex-5 Devices Constraints When Implementing an External Gmii Gmii IOB Constraints 2Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold Timing Ethernet 1000BASE-X PCS/PMA or Sgmii 175 Understanding Timing Reports for Setup/Hold Timing Devices Other Than Virtex-4 or Virtex-5Virtex-4 or Virtex-5 Devices 4Timing Report Setup/Hold Illustration 178 Integrating with the 1-Gigabit Ethernet MAC Core Interfacing to Other Cores MAC Interfacing to Other Cores Integrating with the 1-Gigabit Ethernet MAC Core Virtex-II Pro Devices 182 GTP Virtex-5 LXT and SXT Devices Clkdv Virtex-5 FXT Devices Integrating with the Tri-Mode Ethernet MAC Core Integrating with the Tri-Mode Ethernet MAC Core 186 IOB Logic 188 Ethernet 1000BASE-X PCS/PMA or Sgmii 189 190 8Tri-Speed Ethernet MAC Extended to Use an Sgmii in Virtex-4 192 Ethernet 1000BASE-X PCS/PMA or Sgmii 193 194 Ethernet 1000BASE-X PCS/PMA or Sgmii 195 196 Loopback Power ManagementSpecial Design Considerations Startup Sequencing Special Design Considerations Core with RocketIO Transceiver Loopback 200 Synthesis Using the Simulation ModelImplementing the Design Pre-implementation Simulation Mapping the Design ImplementationXST Verilog Generating the Xilinx Netlist Generating a Bitstream Using the ModelPost-Implementation Simulation Static Timing Analysis Virtex-5 Devices Other Implementation Information Hardware Verification Core Verification, Compliance, and InteroperabilityVerification Simulation 206 Transmit Path Latency Core LatencyCore Latency Latency for 1000BASE-X PCS with TBI Latency for Sgmii Calculating the DCM Fixed Phase Shift Value Requirement for DCM Phase ShiftingFinding the Ideal Phase Shift Value for Your System Appendix C Calculating the DCM Fixed Phase Shift Value Introduction 1000BASE-X State Machines Start of Frame Encoding Even Transmission CaseAppendix D 1000BASE-X State Machines Reception of the Even Case Odd Transmission CaseStart of Frame Encoding Reception of the Odd Case End of Frame Encoding Preamble ShrinkageEnd of Frame Encoding 216 Ethernet 1000BASE-X PCS/PMA or Sgmii 217 218 Rx Elastic Buffer Specifications Rx Elastic Buffers Depths and Maximum Frame SizesRocketIO Rx Elastic Buffers Virtex-II Pro and Virtex-5 Devices Appendix E Rx Elastic Buffer Specifications Rx Elastic Buffers Depths and Maximum Frame Sizes Virtex-4 FX Figure E-2Elastic Buffer Size for all RocketIO families Sgmii Fabric Rx Elastic Buffer For Sgmii / Dynamic Switching TBI Rx Elastic BufferFor 1000BASE-X Idle Character Removal at 1Gbps 1000BASE-X and Sgmii Clock Correction Idle Character Removal at 100 Mbps Sgmii Idle Character Removal at 10 Mbps SgmiiClock Correction Maximum Frame Sizes for Sustained Frame Reception Jumbo Frame ReceptionRocketIO Sgmii Fabric Buffer General Checks Problems with the MdioProblems with Data Reception or Transmission Debugging Guide Problems with Auto-Negotiation Problems in Obtaining a Link Auto-Negotiation DisabledAppendix F Debugging Guide Debugging Problems with a High Bit Error RateSymptoms Problems with a High Bit Error Rate RocketIO Transceiver Specific Checks