Xilinx 1000BASE-X TBI Rx Elastic Buffer

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 223
UG155 March 24, 2008
Rx Elastic Buffers: Depths and Maximum Frame Sizes
R
TBI Rx Elastic Buffer
For SGMII / Dynamic Switching
The Rx Elastic Buffer used for the SGMII or Dynamic Standards Switching is identical to
the method use in “SGMII Fabric Rx Elastic Buffer.”
For 1000BASE-X
Figure E-3 illustrates the Rx Elastic Buffer depth and thresholds when using the Ten-Bit-
Interface with the 1000BASE-X standard. This buffer is intentionally smaller than the
equivalent buffer for SGMII/Dynamic Switching; because a larger size is not required, the
buffer is kept smaller to save logic and keep latency low. Each FIFO word corresponds to a
single character of data (equivalent to a single byte of data following 8B10B decoding).
The shaded area of Figure E-3 represents the usable buffer availability for the duration of
frame reception.
•If the buffer is filling during frame reception, then there are 30-18 = 12 FIFO locations
available before the buffer reaches the overflow mark.
•If the buffer is emptying during reception, then there are 14-2 = 12 FIFO locations
available before the buffer reaches the underflow mark.
Tab le E -2 : Maximum Frame Sizes: Fabric Rx Elastic Buffers
(100ppm Clock Tolerance)
Standard / Speed Maximum Frame Size
1000BASE-X (1 Gbps only) 280000
SGMII (1 Gbps) 280000
SGMII (100 Mbps) 28000
SGMII (10 Mbps) 2800
Figure E-3: TBI Elastic Buffer Size for All Families
3218
30 - Overflow Mark
2 - Underflow Mar
k
TBI
Rx Elastic Buffer
14