Freescale Semiconductor SC140 specifications I2-I0 Interrupt Mask Bits Reflect, Exceptions

Core Control Registers

Table 3-1. Status Register Description (Continued)

Name	Description	Settings
LF2	Loop Flag 2 — When set, indicates that	0 = Hardware loop #3 not enabled
Bit 29	hardware loop #3 is enabled. At the start	1 = Hardware loop #3 enabled
	of an ISR, the SR (including the LF2 bit)
	is pushed onto the software stack and
	the LF2 bit is cleared.
	This bit is cleared at core reset.
LF1	Loop Flag 1 — When set, indicates that	0 = Hardware loop #2 not enabled
Bit 28	hardware loop #2 is enabled. At the start	1 = Hardware loop #2 enabled
	of an ISR, the SR (including the LF1 bit)
	is pushed onto the software stack and
	the LF1 bit is cleared.
	This bit is cleared at core reset.
LF0	Loop Flag 0 — When set, indicates that	0 = Hardware loop #1 not enabled
Bit 27	hardware loop #1 is enabled. At the start	1 = Hardware loop #1 enabled
	of an ISR, the SR (including the LF0 bit)
	is pushed onto the software stack and
	the LF0 bit is cleared.
	This bit is cleared at core reset.
R	Reserved
Bits
26–24
I2–I0	Interrupt Mask Bits — Reflect the
Bits	current interrupt priority level (IPL) of the
						Exceptions	Exceptions
23–21	core. Only non-maskable interrupts or		I2	I1	I0
						Permitted	Masked
	interrupts with an IPL higher than the
	current interrupt mask value can
			0	0	0	IPL 1–7	IPL 0
	interrupt the core. The current IPL of the
	core can be changed under software		0	0	1	IPL 2–7	IPL 0–1
	control.
	At the start of an ISR, the SR (including		0	1	0	IPL 3–7	IPL 0–2
	the interrupt mask bits) is pushed onto
			0	1	1	IPL 4–7	IPL 0–3
	the software stack. The interrupt mask
	bits are changed to the IPL of the
			1	0	0	IPL 5–7	IPL 0–4
	interrupt being serviced.
	The interrupt mask bits are set at core		1	0	1	IPL 6–7	IPL 0–5
	reset.
			1	1	0	IPL 7	IPL 0–6
	For a detailed description of interrupt
	service, refer to Section 5.8, “Exception
			1	1	1	NMI	IPL 0–7
	Processing,” on page 5-46.
			An IPL0 exception is always masked.

SC140 DSP Core Reference Manual 3-3