Index I-1
A
AAU (address arithmetic unit) 1-3, 2-4
ABS A-20
Accelerator 2-5, 6-57
Access width support 2-42
ADC A-22
ADD A-24
ADD2 A-27
ADDA A-29
ADDL1A A-32
ADDL2A A-34
ADDNC.W A-36
Address 2-35
Address generation pipeline stage 5-4
Address modif ier mod es 2-45
linear addressing mode 2-45
modulo addressing mode 2-45
multiple wrap-around modulo addressing
mode 2-47
Address register indirect modes
address modifier modes 2-45
Address registers 2-4, 2-35, 2-37
Addressing modes
PC relative mode 2-40
register direct mode 2-38
register indirect mode 2-38
special address modes 2-41
special mode 2-41
summary 2-43
ADR A-38
AGU
architecture 2-31
arithmetic instruct ions 2-48
block diagram 2-32
programming model 2-34
AGU (address generation unit) 1-3, 2-3, 2-31, 2-34,
2-64
ALU (arithmetic logic unit) 1-3, 2-2
AM (address modification bits) 2-37
AM bits 2-45
AND A-40, A-43
AND.W A-45
Arithmetic instructions on address registers 2-48
Arithmetic saturation mode 2-25
bit 3-6
ASL A-48
ASL2A A-50
ASLA A-51
ASLL A-52
ASLW A-55
ASR A-57
ASRA A-59
ASRR A-60
ASRW A-63
ATS (access type selection) 4-56, 4-60
AWS (access width selection) 4-59
B
B0-B7 (base address registers) 2-36
BEM (big endian memory bit) 3-8
BF A-65
BFD A-67
BFU (bit-field unit ) 2-2, 2-3, 2-12
Bit mask
instructions 2-49
semaphore support instructions 2-50
Bit mask instructions 2-67
BMCHG A-69
BMCHG.W A-69
BMCLR A-75
BMCLR.W A-78
BMSET A-80
BMSET.W A-82
BMTSET A-84
BMTSET.W A-86
BMTSTC A-89
BMTSTC.W A-91
BMTSTS A-94
BMTSTS.W A-96
BMU (bit mask unit) 1-3, 2-4
BRA A-99
BRAD A-101
BREAK A-103
BS (bus selection) 4-56
BSR A-105
BSRD A-107
BT A-109
BTD A-111
C
C (carry bit) 3-7
CACS (comparator A condition selection) 4-56
Carry bit 3-7
CBCS (comparator B condition selection) 4-56
Index