Freescale Semiconductor SC140 specifications Xvi

4-2	JTAG Instructions	. 4-3
4-3	JTAG Scan Paths	. 4-5
4-4	EOnCE Event Types	4-14
4-5	EOnCE Event and Action Summary	4-15
4-6	EOnCE Controller Register Set	4-17
4-7	Event Counter Register Set	4-19
4-8	EDCA Register Set	4-23
4-9	EDCD Register Set	4-24
4-10	Event Selector Register Set	4-26
4-11	Trace Buffer Register Set	4-30
4-12	EOnCE Register Addressing Offsets	4-31
4-13	ECR Description	4-36
4-14	ESR Description	4-38
4-15	EMCR Description	4-41
4-16	EE_CTRL Description	4-46
4-17	Length Control Bits	4-48
4-18	ECNT_CTRL Description	4-51
4-19	EDCA_CTRL Description	4-54
4-20	EDCD_CTRL Description	4-58
4-21	ESEL_CTRL Description	4-62
4-22	Allowed tracing mode combinations	4-66
4-23	TB_CTRL Description	4-67
5-1	Pipeline Example	. 5-3
5-2	Pipeline Stages Overview	. 5-3
5-3	Prefix Instructions	. 5-9
5-4	Conditional IFc Syntax	. 5-9
5-5	Instruction Categories Timing Summary	5-15
5-6	Non-Loop Change-of-Flow Instructions	5-17
5-7	Loop Change-Of-Flow Instructions	5-18
5-8	Number of Cycles Needed by Change-of-Flow Instructions	5-20
5-9	LPMARKA and LPMARKB Bits in Short and Long Loops	5-27
5-10	Loop Control Instructions	5-29
5-11	Stack Push/Pop Instructions	5-34
5-12	Even and Odd Registers	5-34
5-13	Stack Memory Map	5-35
5-14	Stack Move Instructions	5-35
5-15	Working Modes	5-37
5-16	Processing State Change Instructions	5-41
5-17	Processing State Transitions	5-43

xvi SC140 DSP Core Reference Manual