Freescale Semiconductor SC140 specifications Pipeline Example, Pipeline Stages Overview

Pipeline

Table 5-1 shows a typical pipeline flow. For the machine to advance to the next instruction cycle, all of the five operations at the current cycle must be completed.

Table 5-1. Pipeline Example

Instruction Cycle

Operation

1

2

3

4

5

6

7

8

9

10

11

12

Pre-fetch

i1

i2

i3

i4

i5

i6

Fetch

i1

i2

i3

i4

i5

i6

Decode

i1

i2

i3

i4

i5

i6

Address

i1

i2

i3

i4

i5

i6

Generation

Execution

i1

i2

i3

i4

i5

i6

Table 5-2 provides an overview of the operations performed at each stage of the pipeline.

		Table 5-2. Pipeline Stages Overview
Pipeline Stage	Description
Pre-fetch	•	Generate addresses for program fetch
	• Update fetch counter (FC)
Fetch	•	Read fetch set from memory
Dispatch	•	Dispatch instructions
	•	Decode AGU instructions
Address Generation	•	Decode DALU instructions
	• Generate addresses for data load and store operations
	• Perform address calculations: normal and change-of-flow
	• Perform AGU arithmetic instructions
	•	Update AGU registers
Execution	•	Read source operands to DALU
	• Read source register for memory store operations
	• Perform data calculations (multiply and add)
	• Write DALU results to destination registers
	• Write destination register for memory load operations

SC140 DSP Core Reference Manual 5-3