Freescale Semiconductor SC140 specifications Instruction Pipeline Stages

Pipeline

To support parallel execution, the core uses a variable length execution set (VLES) architecture with a static grouping mechanism. Several instructions can be grouped together to form an execution set, which is dispatched to the execution units in parallel. The core contains four ALUs and two AAUs and thus execution set can contain up to four DALU instructions and two AGU instructions with a maximum of eight words. For many instructions, an execution set takes only one clock cycle. For a detailed description of SC140 core instruction timing, see Section 5.3, “Instruction Timing,” on page 5-14.

5.1.1 Instruction Pipeline Stages

Figure 5-1 illustrates the five instruction pipeline stages.

Pre-fetch

Fetch

Dispatch

Address

Generation

Execution

Figure 5-1. Instruction Pipeline Stages

5-2 SC140 DSP Core Reference Manual