Freescale Semiconductor SC140 Status Bit Updates, Instruction Words, MOVE-like Instructions

Programming Rule Notation

7.4.3.2 B Register Aliasing

The B0-7 base registers are the same registers as the R8-15 address registers in the AGU. For example, B0 and R8 have different source syntax and instruction encoding, but they are aliases to the same physical register. The rules always specify the Rn registers. The assembler and simulator detect the programming rules using either alias.

Example 7-1. B Register Aliasing

move.l d0,r8 move.l d1,b0 ;not allowed by G.G.4 - r8 and b0 are the same reg.

7.4.4 Status Bit Updates

In this chapter the programming rules use the notation “affected by” or “affect(s)” to refer to individual status bit sources and destinations, respectively. This notation applies to individual status bits as explicitly stated in each instruction definition in Appendix A.2, “Instructions.” The rules treat status bits as 1-bit registers.

7.4.5 Instruction Words

SC140 instructions can be one, two or three words long. All SC140 instructions have a base size of one word (16-bits). The second and third words of an instruction are called “extension words”.

7.4.6 MOVE-like Instructions

Instructions that access data during the Execute pipeline stage, including:

—All explicit MOVE instructions listed in Table A-10: AGU Move Instructions on page A-16

—VSL instructions listed in Table A-10: AGU Move Instructions on page A-16

—Pop/push instructions listed in Table A-11: AGU Stack Support Instructions on page A-16

—Bit mask instructions listed in Table A-12: AGU Bit-Mask Instructions (BMU) on page A-17 COF instructions that have implicit push/pop operations are not considered MOVE-like instructions.

In this chapter, a subset of this list is relevant if the rule applies to register sources only (POP is not relevant) or register destinations only (PUSH and BMTSTx are not relevant).

7.4.6.1 Address/Data Operands

In this chapter, MOVE-like instructions use pipeline-specific operand notation. “Data” operands refer to actual data being read from a source and written to a destination during the Execute pipeline stage. “Address” operands are read during the Address Generation pipeline stage to determine the address of a data operand in memory, and written during the Address Generation pipeline stage if an address register update is specified by the MOVE-like instruction. Address operands are not written for the (Rn) No Update and address pre-calculation addressing modes. When a programming rule applies to only one operand type, it will be stated in the rule definition. If not stated, the rule applies to both address and data operands of the MOVE-like instruction.

SC140 DSP Core Reference Manual 7-5