Index I-9
Trace unit
control register (TB_CTRL) 4-65
read pointer register (TB_RD) 4-69
register set 4-30
virtual register (TB_BUFF) 4-69
write pointer register (TB_WR) 4-69
TRAP 5-37, A-412
TRSINT (transmit interr u pt) 4-41
TRSMT (transmit) 4-38
TRST (test reset pin) 4-2
True bit 3-6
TSTEQ A-414
TSTEQA.x A-415
TSTGE A-417
TSTGEA.L A-418
TSTGT A-420
TSTGTA A-421
Two’s complement rounding 2-2 3
U
Unsigned arithmetic 2-20
Unsigned integer data format 2-19
Unsigned multiplication 2-20
V
VF3-0 (Viterbi flags 3-0) 3-4
Viterbi decoding support 2-30
VLES (variable length execution set) 1-2
VSL A-422
W
WAIT A-426
Wait processing state 5-44
X
XABA and XABB (data memory address buses) 2-1
XDBA and XDBB (data memory address buses) 2-1,
2-6
Z
ZXT.x A-428
ZXTA.x A-430