Freescale Semiconductor SC140 specifications List of Figures

List of Figures

1-1	Block Diagram of a Typical SoC Configuration with the SC140 Core	. 1-5
2-1	Block Diagram of the SC140 Core	. 2-2
2-2	DALU Architecture	. 2-6
2-3	DALU Data Representations	2-18
2-4	Fractional and Integer Multiplication	2-20
2-5	Convergent Rounding (No Scaling)	2-22
2-6	Two’s Complement Rounding (No Scaling)	2-24
2-7	DMAC Implementation	2-26
2-8	Fractional Double-Precision Multiplication	2-27
2-9	Fractional Mixed-Precision Multiplication	2-28
2-10	Signed Integer Double-Precision Multiplication	2-29
2-11	Unsigned Integer Double-Precision Multiplication	2-30
2-12	AGU Block Diagram	2-32
2-13	AGU Programming Model	2-34
2-14	Modifier Control Register (MCTL) Format	2-37
2-15	Modulo Addressing Example	2-46
2-16	Integer Move Instructions	2-53
2-17	Fractional Move Instructions	2-54
2-18	Bit Allocation in MOVE.L D0.e:D1.e	2-55
2-19	Endian Example	2-56
2-20	Basic Connection between SC140 Core and Memory	2-57
2-21	Memory Organization of Big and Little Endian Mode	2-57
2-22	Data Transfer in Big and Little Endian Modes	2-59
2-23	Multi-Register Transfer in Big and Little Endian Modes	2-61
2-24	Program Memory Organization in Big and Little Endian Modes	2-62
2-25	Instruction Moves in Big and Little Endian Modes	2-63
3-1	Status Register -SR	. 3-2
3-2	Exception and Mode Register (EMR)	. 3-7
4-1	JTAG and EOnCE Multi-core Interconnection	. 4-3
4-2	TAP Controller State Machine	. 4-5
4-3	Cascading Multiple EOnCE Modules	. 4-7
4-4	Reading and Writing EOnCE Registers Via JTAG	. 4-8
4-5	Accessing EOnCE registers through JTAG	. 4-9
4-6	Typical Debugging System	4-10

SC140 DSP Core Reference Manual xiii