Freescale Semiconductor SC140 specifications Highest cycle count of instructions grouped with Call

Models: SC140

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Instruction Timing

change-of-flow occurs to a new execution set spread over two fetch sets, two new fetches must be read from memory.

The subroutine call instructions (JSR, JSRD, BSR, and BSRD) need one free cycle in order to push the return PC and SR onto the stack. Normally, a subroutine call instruction uses one of the idle cycles while the pipeline is filling up so that no stall occurs. However, one stall cycle is added if the instructions that execute in parallel with the subroutine CALL need more cycles than a specific number. In essence, an additional cycle is added to a subroutine call instruction when (Cjn + Cd) ≥ Cj where:

Cjn

Highest cycle count of instructions grouped with CALL

Cj

Cycle count of the non-delayed version of CALL (for example, BSR and BSRD, Cj = 4)

Cd

Cycle count of the set in the delayed slot (if CALL is not a delayed instruction, Cd = 0)

Example 5-7 shows a case when a stall cycle is added.

Example 5-7. Subroutine Call Timing

JSRD

_subr

MOVE.W (R0+2),D0

;

Cj

=

3, Cjn = 2

ADDA

R0,R1

 

;

Cd

=

1

Table 5-8 summarizes the cycle count for change-of-flow instructions. In the Number of Cycles column, Cd represents the length of the delay slot in cycles. The technique of subtracting the cycles of the delay slot instructions from the cycle count of the delayed change-of-flow instruction assumes that the delay slot instructions’ cycles are counted separately. The net count should be zero since the instructions are “hidden” in the delay slot. The minimum number of cycles is specified for the delayed instructions, but only when the number of cycles is small enough for the minimum number of cycles to actually occur. If no number appears in the Minimum Number of Cycles column, the equation in the Number of Cycles column applies, with no minimum.

Table 5-8. Number of Cycles Needed by Change-of-Flow Instructions

Instruction

Number of

Minimum Number

Condition

Cycles

of Cycles

 

 

 

 

 

 

 

 

 

 

 

JMP

3

 

 

 

 

 

 

JMPD

3 – Cd

1

 

 

 

 

 

JSR

3

 

Cjn < 3

 

4

 

Cjn 3

JSRD

1+ Cjn

 

 

BRA, BSR

4

 

 

 

 

 

 

BRAD

4 – Cd

1

 

BSRD

4 – Cd

2

Cjn+Cd < 4

 

1+ C

 

Cjn+Cd 4

 

jn

 

 

Jc/Bc

4

 

Jump is taken.

 

1

 

Jump is not taken.

 

 

 

 

JcD/BcD

4 – Cd

 

Jump is taken.

 

1

 

Jump is not taken.

 

 

 

 

5-20

SC140 DSP Core Reference Manual

Page 200
Image 200
Freescale Semiconductor SC140 Highest cycle count of instructions grouped with Call, Example 5-7. Subroutine Call Timing