Freescale Semiconductor SC140 specifications Core Control Registers, Status Register SR

Models: SC140

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Chapter 3

Control Registers

This chapter describes the core control registers for the SC140 core.

Several bits in these registers are not used, and are marked as reserved. These bits are initialized with a zero value and should be written with a zero value for future compatibility.

3.1 Core Control Registers

The SC140 programming model contains two 32-bit core control registers: a status register (SR) and an exception and mode register (EMR). These registers include dedicated bits for reflecting and controlling different operating modes of the core as well as various status flags.

3.1.1 Status Register (SR)

The SR contains 32 bits. It reflects and controls the following:

Core working mode ( Normal or Exception)

State of the four hardware loops and type of the currently executing loop

Current interrupt priority level (IPL) of the core

Overflow exceptions enabled or disabled

Interrupts enabled or disabled

Viterbi flags

Scaling, rounding, and arithmetic saturation modes

Numeric range of moved data after scaling

Result (true or false) of a condition test

Existence of a carry/borrow generated from the last addition/subtraction operation

Value of last shifted bit during a DALU shift operation

When a subroutine or exception is serviced, the status register is pushed onto the stack. The following instructions implicitly push the SR onto the stack:

JSR/D

BSR/D

Any exception or interrupt implicitly pushes the SR onto the stack, including exceptions that are triggered by the following instructions:

TRAP

SC140 DSP Core Reference Manual

3-1

Page 101
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Freescale Semiconductor SC140 specifications Core Control Registers, Status Register SR