Freescale Semiconductor SC140 specifications Memory Interface, Bit Allocation in MOVE.L D0.eD1.e

Memory Interface

The extension bits of the even data register occupy bits 0 to 8 (bit 8 is the limit bit). The extension bits of the odd register occupy bits 16 to 24 (bit 24 is the limit bit) as described in Figure 2-18.

31	24	16	8	0
	0		0		Memory Long Word

L0

L1

	39	32	16	0
+	extension				D0
+
	extension				D1

Figure 2-18. Bit Allocation in MOVE.L D0.e:D1.e

Moves from memory to an extension are only to single registers. However, they are also 32-bit wide and implicitly assume the bit allocation described above according to the register number (odd or even). For example, move.l $4F42,d3.E is the instruction for moving bits 24:16 from the memory location addressed by $4F42 to the limit bit and extension bits of the odd register d3. See Appendix A, “Move Long Word (AGU) MOVE.L,” , for more information about the moves to and from extension registers.

2.4 Memory Interface

The SC140 core interfaces to memory via the following:

•32-bit program memory address bus (PAB) and 128-bit program memory data bus (PDB)

•32-bit data memory address bus A (XABA) and 64-bit data memory data bus A (XDBA)

•32-bit data memory address bus B (XABB) and 64-bit data memory data bus B (XDBB)

•Control signals such as read and write access strobes as well as access width control

The SC140 does not specify a memory subsystem architecture, only the minimum requirements for correct execution of SC140 code. Listed below are requirements for all memory designs that interface with the SC140 core.

•The SC140 core supports only unified memory designs. Memory is regarded as a single space. There is no distinction between program memory locations and data memory locations. Each memory location possesses a unique address that can be accessible from either the program or data buses. From the core’s perspective, there is only one memory address “a,” which can hold either data or program information.

•Data must be byte-addressable and accessible by the two data memory buses.

•All data width accesses used by the SC140 core must be supported by the memory such as byte (8 bits), word (16 bits), long word (32 bits), or double-long word and four-word (64 bits). One of four control signals will indicate to the memory which access width is needed for each access.

•Multi-byte memory accesses must support both endian modes.

SC140 DSP Core Reference Manual 2-55