Freescale Semiconductor SC140 Comparator B Condition Selection, Comparator a Condition Selection

Models: SC140

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Event Detection Unit (EDU) Channels and Registers

Table 4-19. EDCA_CTRL Description (Continued)

Name

Description

Settings

 

 

 

 

 

 

 

 

CBCS

Comparator B Condition Selection

00

= Equal to EDCA_REFB

Bits 7–6

Used to select one of these four results

01

= Not equal to EDCA_REFB

 

from comparator B:

10

= Greater than EDCA_REFB

 

• Equal to

11

= Less than EDCA_REFB

 

• Not equal to

 

 

 

• Greater than

 

 

 

• Less than

 

 

 

 

 

 

CACS

Comparator A Condition Selection

00

= Equal to EDCA_REFA

Bits 5–4

Used to select one of these four results

01

= Not equal to EDCA_REFA

 

from comparator A:

10

= Greater than EDCA_REFA

 

• Equal to

11

= Less than EDCA_REFA

 

• Not equal to

 

 

 

• Greater than

 

 

 

• Less than

 

 

 

 

 

 

ATS

Access Type Selection — These bits

00

= Read access

Bits 3–2

are used to select the type of memory

01

= Write access

 

access that should be detected by the

10

= Read or write access

 

event detection channel. The possible

11

= Reserved

 

memory access types are:

 

 

 

• Read access

 

 

 

• Write access

 

 

 

• Read or write access

 

 

 

 

 

 

BS

Bus Selection — Used to select which

00

= XABA

Bits 1–0

address bus or buses should be

01

= XABB

 

sampled for comparison by comparator

10

= XABA and XABB

 

A and/or by comparator B. The possible

11

= PC

 

buses that can be chosen by these bits

 

 

 

are PC, XABA, and XABB.

 

 

 

If XABA and/or XABB are the selected

 

 

 

buses, bus XABA is compared to the

 

 

 

EDCA_REFA register while XABB is

 

 

 

compared to the EDCA_REFB register.

 

 

 

If CS bits are set to 11, then setting BS

 

 

 

bits to 10 enables the user to set a

 

 

 

watchpoint on an address when it is not

 

 

 

known whether the address to be used

 

 

 

for accessing memory is on XABA or

 

 

 

XABB. In this case, the user must set

 

 

 

both reference value registers with the

 

 

 

address to be detected.

 

 

 

If the BS bits are set to 10, then the CS

 

 

 

bits must be set to either 10 or 11.

 

 

 

 

 

 

In order to detect a watchpoint on a PC range, one EDCA is enough. In order to detect a watchpoint on a data address range, two EDCAs are required. When configuring two EDCAs to detect a watchpoint to an address range, one EDCA should be configured to detect the range on bus A, and the other EDCA to detect

4-56

SC140 DSP Core Reference Manual

Page 166
Image 166
Freescale Semiconductor SC140 specifications Comparator B Condition Selection, Comparator a Condition Selection