Reference Manual
SC140 DSP Core
SC140 DSP Core Reference Manual
Table of Contents
SC140 DSP Core Reference Manual
Control Registers
SC140 DSP Core Reference Manual
Program Control
Instruction Set Accelerator Plug-In
Programming Rules
Appendix a
SC140 DSP Core Instruction Set
Appendix B
StarCore Registry
Xii
List of Figures
Xiv
List of Tables
Xvi
SC140 DSP Core Reference Manual Xvii
Xviii
List of Examples
SC140 DSP Core Reference Manual
SC140 DSP Core Reference Manual Xxi
Xxii
About This Book
Abbreviation Description
Abbreviations used in this manual are listed below
Abbreviations
ISR
Revision Date Description
Revision History
Target Markets
Chapter Introduction
Architectural Differentiation
Core Architecture Features
Typical System-On-Chip Configuration
SoC DSP expansion area
Variable Length Execution Set Vles Software Model
System expansion area
SC140 platform
Core Architecture Features
Architecture Overview
Chapter Core Architecture
Data Arithmetic Logic Unit Dalu
Block Diagram of the SC140 Core
Data Register File
Address Generation Unit AGU
Multiply-Accumulate MAC Unit
Bit-Field Unit BFU
Bit Mask Unit BMU
Stack Pointer Registers
Enhanced On-Chip Emulator EOnCE
Program Sequencer Unit Pseq
Instruction Set Accelerator Plug-in Isap Interface
Memory Interface
Dalu Architecture
Dalu
Limit EXT
Dalu Programming Model
Data Registers D0-D15
Operand Type Dn.e Dn.h Dn.l
Write to Data Registers
Read from Data Registers
Dalu Arithmetic Instructions MAC
Data Registers Access Width
Operand Type Data Width Bits
Instruction Description
DIV
NEG
Dalu Logical Instructions BFU
Data Shifter/Limiter
Limiting
Scaling
Calculating the Ln Bit
Scaling Example
Ln Bit Calculation
Scaling Mode Bits Defining the Ln bit Calculation
Limiting with the Moves Instructions
Selected Special Six Other Dalu Instructions Mode
Scaling and Arithmetic Saturation Mode Interactions
Limiting Example
10. Scaling and Limiting Interactions
11. Saturation and Rounding Interactions
Dalu Arithmetic and Rounding
Data Representation
Signed Fractional
Data Formats
Signed Fractional Signed Integer Unsigned Integer
Signed Integer
12. Two’s Complement Word Representations
Division
Multiplication
Unsigned Arithmetic
Unsigned Multiplication
Scaling Mode High Portion Low Portion
13. Rounding Position in Relation to Scaling Mode
Rounding Modes
Unsigned Comparison
Convergent Rounding No Scaling
2.6.2 Two’s Complement Rounding
Two’s Complement Rounding No Scaling
14. Arithmetic Saturation Example
Arithmetic Saturation Mode
Fractional Multi-Precision Arithmetic
Multi-Precision Arithmetic Support
Fractional Double-Precision Multiplication
Fractional Mixed-Precision Multiplication
Integer Multi-Precision Arithmetic
10. Signed Integer Double-Precision Multiplication
11. Unsigned Integer Double-Precision Multiplication
Viterbi Decoding Support
AGU Architecture
Address Generation Unit
Unit AAU
Address
Arithmetic
Address Generation Unit
13. AGU Programming Model
AGU Programming Model
Stack Pointer Registers NSP, ESP
Address Registers R0-R15
Base Address Registers B0-B7
Offset Registers N0-N3
Modifier Registers M0-M3
Shadow Stack Pointer Registers
Address Modifier Modes
Modifier Control Register Mctl
17. Address Modifier AM Bits
Address Register Indirect Modes
Addressing Modes
Register Direct Modes
Address Generation Unit
PC Relative Mode
Special Addressing Modes
Memory Access Misalignment
Memory Access Width
Addressing Modes Summary
Access Type Aligned Address
19. Memory Address Alignment
20. Addressing Modes Summary
Special
Address Register Indirect
PC Relative
Reverse-carry Addressing Mode
Linear Addressing Mode
Modulo Addressing Mode
Address Modifier Modes
15. Modulo Addressing Example
Modifier Mj Address Calculation Arithmetic
Multiple Wrap-Around Modulo Addressing Mode
21. Modulo Register Values for Modulo Addressing Mode
23. AGU Arithmetic Instructions
Arithmetic Instructions on Address Registers
Bit Mask Instructions
24. AGU Bit Mask Instructions BMU
Bit Mask Test and Set Semaphore Support Instruction
Semaphore Hardware Implementation
Move Instructions
Example of Normal Usage of the Semaphoring Mechanism
Label BMTSET.W #mask,R0 JT label
MOVE.W
25. AGU Move Instructions
16. Integer Move Instructions
17. Fractional Move Instructions
18. Bit Allocation in MOVE.L D0.eD1.e
Memory Interface
1.1 SC140 Bus Structure
1 SC140 Endian Support
20. Basic Connection between SC140 Core and Memory
Memory Organization
Representation Type Value
Data Moves
26. Data Representation in Memory
22. Data Transfer in Big and Little Endian Modes
Address Data
Multi-Register Moves
Multi-Register Transfer in Big and Little Endian Modes
Instruction Word Transfers
25. Instruction Moves in Big and Little Endian Modes
Memory Access Behavior in Big/Little Endian Modes
Example MOVE.2L D0D1, R0
Example MOVE.L D0.ED1.E, A0
Example MOVE.F D0, R0
Example MOVE.2F D0D1, R0
D6 =
Example VSL.4W D2D6D1D3, R0 + N0
Example VSL.4F D2D6D1D3, R0 + N0
Example VSL.2W D1D3, R0 + N0
Example Push D0 Push D1
Example Push D0
Example BMSET.W #$1234, A0
Data =
Instruction Register Operands Big Little Endian
31. Control Instructions in Big and Little Endian Modes
Status Register SR
Core Control Registers
Status Register Description
Name Description Settings
Describes the various SR bits
Exceptions
I2-I0 Interrupt Mask Bits Reflect
Disable Interrupts Bit When this bit
Overflow Exception Enable Bit
Exception Mode Bit Selects
Reserved
S1-S0 Scaling Mode Bits Specify
Equation Mode
Scaling Mode Bit
Rounding Mode Bit Selects the type
Name Description Settings Arithmetic Saturation Mode Selects
Exception and Mode Register EMR
Exception and Mode Register EMR
EMR Description
Describes the EMR fields
Illegal Execution Set Indicates whether an
Ilst
Clearing EMR Bits
PLL and Clock Registers
Bmclr #$fffb,EMR.L
Example 3-1. Clearing an EMR Bit
Debugging System
Emulation and Debug EOnCE
Signal Name Signal Description
Jtag Interface Signal Descriptions
Overview of the Combined Jtag and EOnCE Interface
Cascading Multiple SC140 EOnCE Modules in a SoC
Jtag Instructions
Jtag Scan Paths
Loadgpr
Select-DR Scan Path Select-IR Scan Path
TAP Controller State Machine Jtag Scan Paths
Enabling the EOnCE Module
Activating the EOnCE Through the Jtag Port
Reading/Writing EOnCE Registers Through Jtag
Debugrequest and Enableeonce Commands
Reading and Writing EOnCE Registers Via Jtag
EOnCE register read capture operation through Jtag
EOnCE register write operation through Jtag
EOnCE Signals Jtag Signals
EOnCE Signals
Main Capabilities of the EOnCE Module
Core Interface
Debug State
EOnCE Dedicated Instructions
Software Downloading
Debug Exception
Executing an Instruction while in Debug State
Software Downloading
Event type Occurs when
EOnCE Events
EOnCE Event Types
Event and Action Summary
EOnCE Actions
EOnCE Event and Action Summary
Event type
EOnCE Controller
EOnCE Enabling and Power Considerations
EOnCE Module Internal Architecture
Transmit Register Update Signal from the TAP Controller
Command Register
Address Monitor and Control Register
Address Control Decoder Logic Receive Register
Event Counter
Event Counter Register Set
Shows a block diagram of the event counter
Event Detection Unit EDU
Address Buses
EE5..0
XDBxx Data Buses
EventD Event0 Event1 Event2 Event5 Count event
EEi
Address Event Detection Channel Edca
Edca Register Set
Event External Event 6,7 Count Event
Data Event Detection Channel Edcd
EventD
Edcd register set is shown below
Optional External Event Detection Address Channels
Event Selector ES
Trace Unit
EE40 ES block diagram is shown in Figure
Event0..Event5 External Event6, Event7 EventD Count event
10. Event Selector Register Set
EOnCE Module Internal Architecture
Trace Buffer TB Off-Core
Change of Flow and Interrupt Tracing
Change of Flow
Trace Unit Programming Model
Writing to the Trace Buffer
Reading the Trace Buffer Tbbuff
11. Trace Buffer Register Set
EOnCE Register Addressing
Offset
12 displays the EOnCE register addressing offsets
12. EOnCE Register Addressing Offsets
EDCA4REFA
Real-Time Jtag Access
Reading or Writing EOnCE Registers Using Core Software
Real-Time Data Transfer
General EOnCE Register Issues
EOnCE Register Addressing
Read/Write Command Specifies
EOnCE Command Register ECR
EOnCE Controller Registers
13 describes the ECR fields
EOnCE Status Register ESR
16 displays the bit configuration of the ESR
Name Description
14 describes the ESR fields
14. ESR Description
Section
DREE3
15 describes the Emcr fields
EOnCE Monitor and Control Register Emcr
15. Emcr Description
Name Description Reserved
Debugerst
EOnCE Transmit Register Etrsmt
EOnCE Receive Register Ercv
EE Signals as Outputs
EE Signals
Detection by the Event Detection Channels
Detecting Entry into Debug State
EE Signals Control Register Eectrl
EE Signals as Inputs
Eeddef
16. Eectrl Description
EE2DEF
Length control bits are described in -17, below
Core Command Register Corecmd
17. Length Control Bits
Length Control Bits Description
PC of the Next Execution Set Pcnext
PC of the Exception Execution Set Pcexcp
PC of Last Execution Set Pclast
PC Breakpoint Detection Register Pcdetect
Event Counter Control Register Ecntctrl
Event Counter Registers
18 describes the Ecntctrl fields
Extended Mode of Operation Bit
18. Ecntctrl Description
Reserved for Test
Events to be Counted Determines
Event Counter Enable Used to
Event Counter Value Register Ecntval
Extension Counter Value Register Ecntext
EC Signals
Address Event Detection Channel Edca
Event Detection Unit EDU Channels and Registers
Edca Control Registers EDCAiCTRL
19 describes the EDCAiCTRL fields
Comparators Selection Used to
Event Detection Channel EDCAi
Comparator a Condition Selection
Access Type Selection These bits
Comparator B Condition Selection
Edca Mask Register EDCAiMASK
Edca Reference Value Registers a and B EDCAiREFA, EDCAiREFB
Edcd Control Register Edcdctrl
Data Event Detection Channel Edcd
20 describes the Edcdctrl fields
20. Edcdctrl Description
AWS
Access Width Selection
Comparator Condition Selection
Access Type Selection The ATS bit
Event Selector Control Register Eselctrl
Event Selector ES Registers
Edcd Reference Value Register Edcdref
Edcd Mask Register Edcdmask
21. Eselctrl Description
Eselctrl fields are described in Table
Event Selector Mask Debug State Register Eseldm
24 displays the bit configuration of Eseldm
Event Selector Mask Debug Exception Register Eseldi
Event Selector Mask Enable Trace Register Eseletb
Trace Buffer Control Register Tbctrl
Event Selector Mask Disable Trace Register Eseldtb
Trace Unit Registers
22. Allowed tracing mode combinations
This mode is usefull only with the Tcount mode
Trace mode
Upon a trace event, trace the counter value Ecntval
Tbctrl fields are described in the following table
Trace Buffer Counter Mode
23. Tbctrl Description
Trace Buffer Extension Counter
Trace Buffer Enable Mode Enables
Trace Loops Mode Enables tracing
Trace Mark Instruction Mode
Trace Issue of Execution Sets Enable
Trace Buffer Register Tbbuff
Trace Buffer Read Pointer Register Tbrd
Trace Buffer Write Pointer Register Tbwr
Trace Unit Registers
Pipeline
Chapter Program Control
Illustrates the five instruction pipeline stages
Instruction Pipeline Stages
Pipeline Stages Overview
Pipeline Example
Instruction Cycle Operation
Pipeline Stage Description
Address Generation
Instruction Pre-Fetch and Fetch
Instruction Dispatch
Example 5-1. Four SC140 Instructions in an Execution Set
Instruction Grouping
Execution
Instruction Grouping Methods
Grouping Types
Prefix Grouping
Serial Grouping
Two-Word Prefix
Prefix Types
One-Word Low Register Prefix
Conditional Execution
For example
Prefix Instructions
Prefix Selection Algorithm
Assembly Syntax Meaning
Low Register Prefix Selection Algorithm
Instruction Reordering Within an Execution Set
Example 5-5. Set of 2 Two-word Instructions Requiring a NOP
Example 5-4. Conditional Vles Having Two Subgroups
Instruction Timing
Instruction Categories Timing Summary
Sequential Instruction Timing
Move Instruction Timing
Dalu Instruction Timing
Bit Mask Instruction Timing
Compare Shift Test
Non-Loop Change-of-Flow Instructions
Example 5-6. Delayed Change-of-Flow and Its Delay Slot
Change-Of-Flow Instruction Timing
Loop Change-Of-Flow Instructions
Direct, PC-Relative, and Conditional COF
COF Execution Cycles
Delayed COF
Highest cycle count of instructions grouped with Call
Example 5-7 shows a case when a stall cycle is added
Number of Cycles Needed by Change-of-Flow Instructions
Example 5-7. Subroutine Call Timing
Memory Access Timing
Memory Access Examples
Example 5-8. Parallel Execution of Two Move Instructions
MOVE.L
Memory Stall Conditions
Implicit Push/Pop Memory Timing
Loop Start Address Registers SAn
Hardware Loops
Loop Programming Model
Status Register SR Loop Flag Bits
Loop Notation and Encoding
Loop Counter Registers LCn
Lpmarka and Lpmarkb Bits in Short and Long Loops
Loop Initiation and Execution
Loop Type
Location Functionality
Loop Iteration and Termination
Loop Nesting
10 lists the loop instructions
Loop Control Instructions
10. Loop Control Instructions
Instruction Operation
Example 5-14. Short Loop, Two Execution Sets
Example 5-13. Long Loop Disassembly
Example 5-12. Long Loop
Example 5-16. Nested Loop
Following is an example of a nested loop
Example 5-15. Short Loop, One Execution Set
1 SC140 Single Stack Memory Use
Stack Support
Loop Timing
Shows the stack structure
2 SC140 Dual Stack Memory Use
11. Stack Push/Pop Instructions
Stack Support Instructions
12. Even and Odd Registers
Even Register De File Odd Register Do File
Shadow Stack Pointer Registers
Addressing Mode Description
13. Stack Memory Map
14. Stack Move Instructions
Fast Return from Subroutines
Exception Working Mode
Normal Working Mode
Working Mode EXP bit Active SP
Working Modes
Dual-stack Rtos
Typical Working Mode Usage Scenarios
From Exception to Normal mode
Working Mode Transitions
From Normal to Exception mode
Single-stack Rtos
Working Modes
16. Processing State Change Instructions
Processing States
Processing State Change Instructions
Processing State Transitions
10. Core State Diagram
Execution State
Reset Processing State
17. Processing State Transitions
Processing State Transitions Description
Wait Processing State
18. Exit Wait Processing State due to an Interrupt or NMI
Stop Processing State
Exception Processing
11. Core-PIC Interface
SC140
Programming Exception Routine Addresses
Interrupt Vector Address
Vector Base Address Register
Exception Address Priority Type Description Offset Highest
Return From Exception Instructions
19. Exception Vector Address Table
Non-Maskable Interrupts NMI
Maskable Interrupts
Internal Exceptions
Interrupt Priority Level
Illegal Execution Set
Illegal Exception
Illegal Instruction
Dalu Overflow
Exception Interface to the Pipeline
Trap Exception
Debug Exception
Exception Timing
Exception Mode Execution
20. Exception Pipeline
Example 5-17. Basic Exception Timing
Exception Processing
12 provides a flow chart for Example
21. Pipeline Example
Introduction
Instruction Set Accelerator Plug-In
Single Isap
Isap SC140 Schematic Connection
Data Memory
SC140Core
Multiple Isap
Core to Multiple Isap Connection Schematic
Isap instructions and instruction encoding
Isap Memory Access
Isap Encoding Fields
Binary Encoding Words Bits
To understand this, look at the following lines of code
Example 6-1. Isap memory access
ISAP-core register transfers
Following line of code
Immediate Data Transfer to Isap registers
Example 6-2. ISAP-Core register transfers
Example 6-3. ISAP-Core register transfers
Identification of Isap instructions
Core Assembly Syntax with an Isap
Working with One Isap
Vles that uses an implicit Isap ID string
One Isap in a Multi-Line Vles
Working with Multiple ISAPs
One Isap in a Single-Line Vles
Example 6-5. Multiple Isap coding
An Example of the Definition Flexibility of an Isap
Multiple ISAPs in a Multi-Line Vles
Example 6-7. Conditional Execution Example
Example 6-6. Conditional Execution Example
Isap Functions that Interact With the Core
Programming Rules
Rules for implicit AGU instructions
Grouping rules for explicit Isap instructions
D.2, D.3
Sequencing rules for T bit update
Programming Rules
Vles Grouping Semantics
Vles Sequencing Semantics
Vles Grouping Semantics
Grouping Rules
SC140 Pipeline Exposure
Programming Rule Notation
Register Read/Write
Sequencing Rules
Instruction Words
Status Bit Updates
MOVE-like Instructions
Register Aliasing
Delay Slot
Delayed COF Instructions
AGU Arithmetic Instructions
Change-Of-Flow Destinations
Static Programming Rules
Enabled Loop
Hardware Loops
Hardware Loop Detection
Rule G.G.1
General Grouping Rules
Rule G.G.2
Rule G.G.3
Example 7-5 Duplicate PC Destinations
Rule G.G.4
Example 7-6 Duplicate Address Pointer Register Destinations
Example 7-7 Duplicate Stack Pointer Destinations
Example 7-8 Duplicate Register Destinations
Rule G.G.4 Exceptions
Example 7-9 Duplicate SR/EMR Register Destinations
Example 7-10 Duplicate Status Bit Destinations
Rule G.G.5
Prefix Grouping Rules
Following rules only apply to prefix-grouped Vles
Example 7-15. Dalu Register Use Exceeds Four Times
Example 7-17 Two-Word Instructions Exceed Two
Rule G.P.1
Example 7-16 Vles Extension Words Exceed Two
Rule G.P.4
Rule G.P.3
Rule G.P.5
Example 7-18. Vles Has Mutually Exclusive Instructions
Rule G.P.7
Rule G.P.6
Example 7-20. Data Source Use of Nn and Mn Registers
Example 7-21. IFc Having Two Subgroups
Example 7-24. Isap instructions in same IFc group
Rule G.P.8
Rule G.P.9
Example 7-25. Mctl Write to R0-R7 Use
AGU Rules
Rule A.1
Example 7-26. Rn, Nn, Mn Write to AGU Use
Rule A.2
Rule A.3
Example 7-28. LCn Write to MOVE-like Use
Rule A.4
Example 7-27. Rn or Nn Write to MOVE-like Use
Example 7-29. Nmid Update to EMR Read
Delayed COF Rules
Example 7-30. Instructions in a Delay Slot
Rule A.7
Example RTE/D with SR Updates
Example 7-31. Instructions in a Rted Delay Slot
Rule D.2
Rule D.3
Rule D.5
Rule D.4
Rule D.5a
Rule D.6
Rule D.8
Status Bit Rules
Rule D.9
Rule T.1
Rule T.2.b
Rule T.2.a
Rule T.2.c
Rule SR.2
Static Programming Rules
Example 7-43. SR Write to SR Status Bit Use
Rule SR.4
Example 7-44. SR Write to SR Status Bit Update
Rule SR.3
Rule SR.4a
Example 7-45. Dovf Update to SR Read or Write
Example 7-46. Dovf Update grouped with Move-like SR updates
Rule SR.7
Loop Nesting Rules
Rule L.N.1
DI and EI DOENn and DOENSHn
Rule L.N.3
Rule L.N.2
Example 7-49. Nested Loops with Ordered Index
Example 7-50. Nested DOENn/DOENSHn Instructions
Example 7-53. Changing a loop type
Example 7-52. Loopend between Doen and Loopend
Rule L.L.1
Loop LA Rules
Rule L.L.2
Example 7-54. Instructions at the End of Long Loops
Rule L.L.4
Rule L.L.3
LA of a short loop cannot be at LA-1 of a long loop
Example 7-56. Instructions in Short Loops
Rule L.L.5
Loop Sequencing Rules
Rule L.L.6
Rule L.D.1
Rule L.D.5
Rule L.D.3
Rule L.D.6
Example 7-60. LCn Write at the Start of Short Loop n
Rule L.D.9
Rule L.D.7
Rule L.D.8
Rule L.C.1
Loop COF Rules
Rule L.C.2
Rule L.C.3
Example 7-68. Bc/Jc at LA-3 of a Long Loop
Rule L.C.5
Bc or Jc instruction is not allowed at LA-3 of a long loop
Example 7-69. Loop COF Destination in the Same Loop
Rule L.C.7
Rule L.C.10
Rule L.C.9
Example 7-70. Loop COF at End of Nested Long Loops
Example 7-71. Subroutine Call to End of Loops
Rule L.C.11
General Looping Rules
Rule L.C.12
Rule L.G.3
AGU Dynamic Rules
Dynamic Programming Rules
Rule L.G.5
Rule A.2a
Rule A.5
Memory Access Rules
Rule A.6
Rule D.7
Loop Rules
RAS Rules
Rule J.4
Rule L.N.6
Rule Detection Across COF Boundaries
Example 7-83. A.2 from a Delay Slot to a COF Destination
Cycle-Based COF Rules
Example 7-82. SR.2 Across a COF Boundary
VLES-Based COF Rules
Rule Detection Across Exception Boundaries
Example 7-85. EMR access at the start of an exception
Rule SR.2a
Rule SR.4b
Example 7-86. Mctl Write to R0-R7 Use
Rule A.1a
Programming Guidelines
COF destination cannot be a delay slot
Rule J.1
Rule J.2
Good Programming Practices
Rules Not Detected Across COF Boundaries
Source Code Practices
Rule J.5
Binary Code Practices
Software Development Practices
Lpmark Rules
Lpmark Instruction Type
Dynamic Programming Rules
Static Programming Rules
General Grouping Rules
Prefix Grouping Rules
Loop LA Rules
Loop Nesting Rules
Lpmark Rule L.L.3
Lpmark Rule L.L.2
Lpmark Rule L.L.5
Example 7-93. Active LCn Write at the End of Long Loops
Lpmark Rule L.L.6
Loop Sequencing Rules
Lpmark Rule L.D.2 + L.D.3
Lpmark Rule L.D.6
Lpmark Rule L.C.2
Loop COF Rules
COF instructions are not allowed at LPB of a long loop
Example 7-97. Active LCn Read at the Start of a Loop
Example 7-99. Bc/Jc at the Start of a Loop
Lpmark Rule L.C.3 + L.C.5
Example 7-98. COF Instructions at LPB of a Long Loop
Lpmark Rule L.C.10
Lpmark Rule L.C.9
Example 7-100. Loop COF at End of Nested Long Loops
Example 7-101. Subroutine Call to End of Loops
Rule Detection Across Exception Boundaries
Lpmark Programming Guidelines
General Looping Rules
Lpmark Rule L.C.1
Example 7-104. COF Destination to Loop Delay Slots
NOP Definition
Is encoded as
Grouping Examples
Is assembler mapped to the IFF prefix and encoded as
Is assembler mapped to the IFT prefix and encoded as
Is encoded ignoring the NOP subgroup as
NOP Definition
Appendix a SC140 DSP Core Instruction Set
Convention Definition
Conventions
Table A-1. Instruction Conventions
Table A-3. Register Abbreviations
Table A-2. Operations Syntax
Operator Description
Abbreviation Register Name
Table A-4. Assembler Syntax
Brackets as Isap indicators
Brackets as address indicators
Table A-5. Addressing Mode Notation for the EA Operand
Addressing Mode Notation
Table A-6. Addressing Mode Notation for the ea Operand
Addressing Mode Definition Notation in Instruction Field
Definition for the field is
Data Representation in Memory for the Examples
Encoding Notation
Prefix Word Encoding
Instruction Fields
Instruction Formats and Opcodes
Aaa
Ccc
If true D0, D2, A0, if false D1, D3, A1
Example, 2-w prefix + 2 grouped instruction words, aaa =
If true, all the set
Prefix Words Cycles Type
First execution set of the loop
Last, or to last-1 Example
High data register is used for the op3 field E3 is set
High data register is used for the op1 field E2 is set
DSP Core Instruction Set
Instruction Sub-types
Instruction Types
Table A-7. Dalu Arithmetic Instructions MAC
Table A-8. Dalu Logical Instructions BFU
Table A-9. AGU Arithmetic Instructions
Table A-11. AGU Stack Support Instructions
Table A-10. AGU Move Instructions
Table A-13. AGU Non-Loop Change-of-Flow Instructions
Table A-12. AGU Bit-Mask Instructions BMU
Table A-16. Prefix Instructions
Table A-15. AGU Program Control Instructions
Instruction Definition Layout
Inst
Instructions
ABS
Instruction
Single Source/Destination Data Register
Add Long With Carry Dalu
ADC
Dc + Dd + C → Dd
ADC Dc,Dd
Register/Memory Address Before
Dc,Dd Data Register Pairs
Add Dalu
ADD
Operation Assembler Syntax
Add d0,d1,d2
Add d1,d0,d2
#u5
Da,Db
Da,Da Data Register Pairs
Add2 d0,d1
ADD2
Add Two 16-Bit Values Dalu
Single Source Data Register
JJJ
Add AGU
Adda
Adda #u5,Rx
Adda #s16,rx,Rn
Address Register
Adda r0,r1
#s16
Rrrr AGU Source Register
AGU Source/Destination Register
Source Operand AGU
ADDL1A Add With One-Bit Arithmetic Shift Left ADDL1A
Addl1a r0,r1
Rx1 + Rx → Rx
ADDL1A rx,Rx
Addl2a r0,r1
ADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2A
Rx2 + Rx → Rx
ADDL2A rx,Rx
ADDL2A rx,Rx
Add Without Changing ADDNC.W
ADDNC.W
Carry Bit Dalu
Addnc.w #$ca3e,d1,d2
Instruction Words Cycles Type
Add and Round Dalu
ADR
Adr d3,d4
RndDa + Dn → Dn
ADR Da,Dn
#0u16,Da,Dn
Bitwise and Dalu
#u16$0000,Da,Dn
Da,Dn
#$ff2e0000,d2,d1
D2,d1
#$0ff2e,d2,d1
#u16
#0u16
#u16$0000
#u16 DR.L → DR.L
#$a70e,d1.h
#u16 DR.H → DR.H
#u16,DR.L
Cycles Type Opcode
Data/Address Register
AND.W #u16,SP-u5
AND.W #u16,Rn
AND.W #u16,a16
AND.W #u16,SP+s16
And.w #$54a1,r7
S16
A16
Asl d0,d1
ASL
Da 1→ Dn
ASL Da,Dn
ASL Da,Dn
Asl2a r0
ASL2A
Rx2 → Rx
ASL2A Rx
Asla r0
Asla
Rx1 → Rx
Asla Rx
Multiple-Bit Arithmetic Shift Left Dalu
Asll
Asll #u5,Dn
Asll Da,Dn
Asll d0,d1
Asll
Word Arithmetic Shift Left 16 Bits Dalu Aslw
Aslw
Aslw d0,d1
Da16 → Dn
Aslw Da,Dn
Asr d5,d3
ASR
Da1 → Dn
ASR Da,Dn
Register/Memory Address Before After
Asra Rx
Asra
Asra r2
Multiple-Bit Arithmetic Shift Right Dalu
Asrr
Asrr d3,d5
Asrr #$3,d5
#u5
Asrw Da,Dn
Asrw d5,d0
Asrw Da,Dn
Branch If False AGU
If T==0, then PC + displacement → PC
BF lbl
BF label
Instruction Words Cycles1 Type Opcode
Displacement label
BFD
BFD Branch If False Using a Delay Slot AGU Operation
BFD lbl
BFD label
Label Displacement
~C1.Hi → C1.Hi i denotes bits=1 in #u16
Bmchg
~C1.Li → C1.Li
~DR.Hi → DR.Hi
Control Registers
Bmchg #$f0f0,d1.h
Clears the Ln bit in the destination data register
Iiiiiiiiiiiiiiii 16-bit unsigned immediate data
Bit-Masked Change a
BMCHG.W
BMCHG.W #u16,SP-u5
Bmchg.w #$661f,$800c
Bit signed SP address offset
Bmclr #u16,C1.H
Bmclr Bit-Masked Clear a 16-Bit Operand BMU Bmclr Operation
Bmclr #u16,C1.L
Bmclr #u16,DR.H
Bmclr #$b646,d7.l
#u16
Bit Operand in Memory BMU Operation Assembler Syntax
BMCLR.W
Bit-Masked Clear a
BMCLR.W #u16,SP-u5
Bmset #u16,C1.L
Bmset #u16,C1.H
Bmset #u16,DR.H
Bmset #u16,DR.L
Bmset #$2436,d1.l
Bit Operand in Memory BMU
BMSET.W
$800C
Bmset.w #$f111,$800c
Register/Memory Address Before Immediate
Bmtset #$111f,d1.l
Bmtset
Bmtset #u16,DR.H
Bmtset #u16,DR.L
Bmtset #$4238,d4.l
Bit-Masked Test and Set a BMTSET.W
BMTSET.W
Bmtset.w #$4328,$c
BMTSET.W #u16,SP-u5
Bmtstc #$8a59,d7.h
Bmtstc
$0$0024A60000 $00E40000
BMTSTC.W #u16,SP-u5
BMTSTC.W
BMTSTC.W #u16,SP+s16
BMTSTC.W #u16,Rn
Bmtstc.w #$8A59,r0
BMTSTC.W #u16,SP-u5
Bmtsts #u16,C1.L
Bmtsts
Bmtsts #u16,DR.H
Bmtsts #u16,DR.L
Bmtsts #$24a6,d7.h
BMTSTS.W #u16,SP-u5
BMTSTS.W
BMTSTS.W #u16,SP+s16
BMTSTS.W #u16,Rn
Bmtsts.w #$0428,r0
BMTSTS.W #u16,SP-u5
BRA
PC + displacement → PC
Branch AGU
BRA label
AAAAAAAAAA0
Source Code Comments
Brad
Brad label
$0000 000A $0000 000E
Break
PC + displacement → PC
Break label
→ LFn
Encoding is the displacement with bit
Branch to Subroutine AGU
BSR
Status and Conditions Changed by Instruction None Example
Bsr label
BSR
Bsrd label
PC + displacement → PC, next* PC→RAS
Next* PC → SP SR → SP + 4 SP + 8 → SP
Bsrd label
Branch If True AGU
If T==1, then PC + displacement → PC
BT lbl
BT label
Register/Memory Address Before BT After
BTD
BTD Branch If True Using a Delay Slot AGU Operation
BTD lbl
BTD label
$0035 $0000 $0006 $002A $001A $0016
Count Leading Bits Dalu
CLB
Clb d3,d7
CLB Da,Dn
CLB Da,Dn
Clear a Data Register Dalu
CLR
Clr d1
→ Dn
Source Data Register
Destination Data Register
Compare for Equal Dalu
Cmpeq
Cmpeq d2,d3
If Da == Dn, then 1→ T, else 0 → T
118
CMPEQ.W Compare for Equal Dalu
CMPEQ.W
Cmpeq.w #$5,d3
CMPEQ.W #u5,Dn
CMPEQ.W
Cmpeqa r1,r2
Cmpeqa Compare for Equal AGU Cmpeqa Operation
If rx == Rx, then 1 → T, else 0 → T
Cmpeqa rx,Rx
Cmpeqa rx,Rx
Compare for Greater Than Dalu
Cmpgt
Cmpgt d2,d3
Dn Da → T
124
Cmpgt.w #$8002,d2
CMPGT.W
CMPGT.W #u5,Dn
CMPGT.W #s16,Dn
CMPGT.W #u5,Dn
Compare for Greater Than AGU Cmpgta
Cmpgta
Cmpgta r2,r3
Rx rx → T
Cmpgta rx,Rx
Unsigned Compare for Higher Dalu Cmphi
Cmphi
Cmphi d1,d0
Cmphi Da,Dn
130
Unsigned Compare for Higher AGU Cmphia
Cmphia
Cmphia r0,r1
Cmphia rx,Rx
Cmphia rx,Rx
Continue to the Next Loop Iteration AGU
Cont
Label
Label
Cycles1 Type Opcode
Contd label
Contd
Cycles1 Type
Debug
Enter Debug Mode AGU
Debug
Debugev
Signal a Debug Event AGU Debugev
Decrement a Register AGU
Deca
Deca r0
Rx 1 → Rx
Bit unsigned immediate data = 1, set by the assembler
Deceq Dn
Deceq d7
Dn 1 → Dn if Dn==0, then 1→ T, else 0 → T
142
Deceqa r0
Deceqa Decrement and Set T If Equal Zero Deceqa
Rx 1 → Rx if Rx==0, then 1 → T, else 0 → T Deceqa Rx
Deceqa Rx
Example decge
Decge
Dn 1 → Dn Dn≥0 → T
Decge Dn
SC140 DSP Core Reference Manual 145
Decgea r4
Decgea
Rx 1 → Rx Rx ≥ 0 → T
Decgea Rx
Decgea Rx
SR19 Set disable interrupt bit
Determines execution working mode
→ DI
SR18
Page
Divide Iteration Dalu
DIV
If Dn39 ⊕ Da39 =
Then 2 * Dn + C + Da & $FF Ffff 0000 → Dn
Div d2,d1
DIV Da,Dn
Dmacss d2,d3,d5
Dmacss
Dn16 + Dc.H * Dd.H → Dn
Dc signed, Dd signed
Dmacss Dc,Dd,Dn 1 1
Dmacsu d2,d3,d5
Dmacsu Multiply Signed By Unsigned and Dmacsu
Accumulate With Right Shifted Data Register Dalu
156
Doen2 d0
Do Enable Long Loop AGU
DOENn #u6
DOENn #u16
#u6
Loop Identifier
Doensh2 d0
Do Enable Short Loop AGU DOENSHn
DOENSHn #u6
DOENSHn #u16
$00E4 $A0E4
Dosetup1 label
Setup Long Loop DOSETUPn
PC + displacement → SAn
DOSETUPn label
Encoding is the displacement with
→ DI
SR19 Clears disable interrupt bit
164
Bitwise Exclusive or Dalu
EOR
Eor d4,d5
Da ⊕ Dn → Dn
EOR Da,Dn
EOR #u16,DR.H
Eor #$5,d5.l
EOR #u16,DR.L
EOR #u16,DR.L EOR #u16,DR.H
Bitwise Exclusive or on
EOR.W
Eor.w #$aaaa,r0
Extract Extract Signed Bit Field Dalu
Extract
Extract #$c,#$e,d2,d4
Extract #U6,#u6,Db,Dn
Jjj Single Source/Destination Data Register
Extractu Extract Unsigned Bit Field
Extractu
Extractu #$c,#$e,d2,d4
Extractu #U6,#u6,Db,Dn
Extractu #U6,#u6,Da,Dn
IADDNC.W #s16,Dn
Iaddnc.w #$a002,d2
If T == Then execute group/subgroup
Conditionally Execute a Group or Subgroup Prefix IFc
Else treat as NOP If T == Then execute group/subgroup
Else treat as NOP Execute group/subgroup unconditionally
Ccc Conditional execution of the entire execution set
Ift move.w #$ffff,d0
Illegal
Illegal
Imac d4,d5,d6
Imac
Dn ± Da.L * Db.L → Dn
Imac ±Da,Db,Dn
Accumulation Notation
Imac -d4,d5,d6
182
Imaclhuu Da,Db,Dn
Dn + Da.L * Db.H → Dn
Imaclhuu Da,Db,Dn
Integer Multiply Accumulate
Imacus
Unsigned By Signed Dalu Operation Assembler Syntax
Imacus d3,d4,d0
$0002 x -64 $FFC0 -128 $FF80 +0 $0000 -128 $FF80
Integer Multiply Dalu
Impy
Da.L * Db.L → Dn
Impy Da,Db,Dn
D1,D1 D3,D3 D5,D5 D7,D7
IMPY.W #s16,Dn
Impy.w #$fffe,d3
#s16 * Dn.L → Dn
+16
Integer Multiply Upper Impyhluu
Impyhluu
Impyhluu d4,d3,d0
Da.H * Db.L → Dn
Impyhluu Da,Db,Dn
Impysu d3,d5,d1
Impysu
Impysu Da,Db,Dn
Register Bit Name Description Address
Impysu Da,Db,Dn
Impyuu Da,Db,Dn
Impyuu
Impyuu d5,d3,d1
196
INC Increment a Data Register By One Dalu Operation
INC
Inc d0
INC Dn
Inc d15
INC.F Dn
Inc.f d15
Dn + $0000010000 → Dn
INC.F Dn
Increment Register AGU
Inca
Inca r0
Rx + 1 → Rx
Inca Rx
Insert Bit Field Dalu
Insert
Insert #12,#22,d6,d7
Insert #U6,#u6,Db,Dn
Insert #U6,#u6,Db,Dn
JF lbl
Jump If False AGU
JF label
JF Rn
Bit absolute long address
JFD Rn
JFD
JFD label
$00E0 $00 0000 $0000 $00 0000 002A $00 0000 001A
Jump AGU
JMP
Jmp label
JMP label
JMP label
Jmpd
Jump Using a Delay Slot AGU
Example jmpd lbl
Jmpd label
AaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAAA
Jump to Subroutine AGU
JSR
Jsr r6
JSR label
Absolute long address
Next* PC → RAS Rn → PC
Example jsrd r6
Jsrd label
Jsrd Rn
Jsrd label
Jt r0
Jump If True AGU
JT label
JT Rn
JT label
JTD
Jump If True Using Delay Slot AGU
Example jtd r0
JTD label
JTD label
If LCn Then SAn → PC
LPMARKx End-of-Loop Mark Prefix LPMARKx Operation
LCn 1 → LCn Else next PC → PC → LFn If LCn Then SAn → PC
LCn 1 → LCn Else next PC → PC → LFn → SLF
Table A-17. Combinations of LPMARKx Use
Status and Conditions that Affect Lpmark Execution
LFn
LCn Description
Prefix Formats and Opcodes
Status and Conditions Changed by Lpmark Execution
Insertion of lpmarkb by assembler
Instruction Disassembled Instruction Comments
Multiple-Bit Bitwise Shift Left Dalu
Lsll
Lsll d4,d2
Lsll Da,Dn
$00E4 $0$FF 8765
Bitwise Shift Right One Bit Dalu
LSR
Lsr d4
Dn1 → Dn 0 → Dn39
Bitwise Shift Right By One Bit AGU
Lsra
Lsra r2
Rx1 → Rx 0 → Rx31
Multiple-Bit Bitwise Shift Right Dalu
Lsrr
Lsrr Da,Dn
Lsrr #u5,Dn
Before After
Lsrr d4,d2
Bit unsigned immediate data
Word Bitwise Shift Right Dalu
Lsrw
Lsrw d4,d2
Lsrw Da,Dn
Lsrw Da,Dn
Signed Fractional Multiply-Accumulate Dalu
MAC
Mac d4,d5,d6
MAC #s16,Da,Dn
Mac #$1000,d5,d6
SC140 DSP Core Reference Manual 235
Macr d4,d5,d6
Macr
RndDn ± Da.H * Db.H → Dn
Macr ±Da,Db,Dn
000 0000 0000 1000 $0008 Instruction Formats and Opcodes
238
Macsu d0,d1,d4
Macsu
Dn + Dc.H * Dd.L → Dn
Macsu Dc,Dd,Dn
111 1111 1111 1111 $FFFF Instruction Formats and Opcodes
Macus Dc,Dd,Dn
Macus
Dn + Dc.L * Dd.H → Dn
Macus Dc,Dd,Dn
Fractional Multiply-Accumulate
Macuu
Unsigned By Unsigned Dalu Operation Assembler Syntax
Macuu d2,d3,d1
Macuu Dc,Dd,Dn
PC → trace buffer
Mark
Push the PC into the Trace Buffer AGU Mark
Transfer Maximum Signed Value Dalu
MAX
Max d0,d4
If Dg Dh, then Dg → Dh
Max2 d0,d4
MAX2
If Dg.H Dh.H, then Dg.H → Dh.H
If Dg.L Dh.L, then Dg.L → Dh.L
00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 248
If Da.L Db.L, then 0 → VFn, Da.L → Db.L
MAX2VIT
Else 1 → VFn
MAX2VIT Da,Db
Max2vit d4,d2
Maxm Dg,Dh
Maxm Transfer Maximum Absolute Value Dalu Maxm Operation
Maxm d2,d6
00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 252
Transfer Minimum Signed Value Dalu
MIN
Min d1,d5
MIN Dg,Dh
Move Two Fractional Words from MOVE.2F
MOVE.2F
Memory to a Register Pair AGU
Description
MOVE.2F EA,DaDb
DaDb Data Register Pairs
Move.2l d0d1,r0
MOVE.2L
Da,Db ↔ EA
MOVE.2L DaDb,EA MOVE.2L EA,DaDb
Read/Write Notation
Move.2w d0d1,r0
MOVE.2W
EA ↔ DaDb
MOVE.2W EA,DaDb MOVE.2W DaDb,EA
$FF Ffff AF44
Move Four Fractional Words from MOVE.4F
MOVE.4F
Memory to a Register Quad AGU
EA → DaDbDcDd
DaDbDcDd Data Register Quad
Move.4f r0,d0d1d2d3
MOVE.4W EA,DaDbDcDd MOVE.4W DaDbDcDd,EA
MOVE.4W
EA ↔ DaDbDcDd
Move.4w d0d1d2d3,r0
Byte Move AGU
MOVE.B
MOVE.B DR,ea
Move.b d3,r7+$3
MOVE.B SP+s15,DR
MOVE.B DR,SP+s15
MOVE.B a16,DR
S15
A32
To/from Memory AGU Operation Assembler Syntax
MOVE.F
Move Fractional Word
MOVE.F Db,ea
Move.f $54,d10
MOVE.F SP+s15,Db
MOVE.F #s16,Db MOVE.F a16,Db
SC140 DSP Core Reference Manual 271
Move Long Word AGU
MOVE.L
General Registers
Cccc
#u32
#s32
MOVE.L Da.EDb.E,SP+s15
MOVE.L SP+s15,De.E
MOVE.L SP+s15,Do.E
Move.l d0.ed1.e,$1224
MOVE.L a32,De.E
MOVE.L Da.EDb.E,a32
Da.EDb.E ff Data Register Extension Pair
Data Register
278
Move Long AGU
MOVE.L a16,C4 MOVE.L C4,a16
MOVE.L a32,DR MOVE.L DR,a32
MOVE.L Rn+u3,DR MOVE.L DR,Rn+u3
MOVE.L Rn+s15,DR MOVE.L DR,Rn+s15
MOVE.L SP+s15,C4 MOVE.L C4,SP+s15
Move.l d0,r0
MOVE.L EA,DR MOVE.L DR,EA
Read/Write Notation
Rrr Address Register
Unsigned 3-bit offset
MOVE.W #s16,C4
MOVE.W #s7,DR
MOVE.W #s16,a16
MOVE.W #s16,SP-u5
Move.w #$0050,r7
MOVE.W #s7,DR MOVE.W #s16,C4
Sa16
#s7
Move Integer Word AGU
MOVE.W
MOVE.W a32,DR MOVE.W DR,a32
MOVE.W a16,C4 MOVE.W C4,a16
MOVE.W Rn+s15,DR MOVE.W DR,Rn+s15
MOVE.W Rn+u3,DR MOVE.W DR,Rn+u3
MOVE.W Rn+Rr,DR MOVE.W DR,Rn+Rr
MOVE.W Rn,C3 MOVE.W C3,Rn
Move.w d1,r7+4
MOVE.W a32,DR MOVE.W DR,a32
Write
Sss0
Movet r0,r1
MOVEc Conditional Address Register Move AGU MOVEc Operation
Movet Rq,Rn
Movef Rq,Rn
Qqq Address Register
MOVES.2F DaDb,EA
MOVES.2F Move Two Fractional Words to MOVES.2F
DaDb → EA
$7FFF $7EAC
MOVES.4F DaDbDcDd,EA
Moves.4f d0d1d2d3,r0
DaDbDcDd → EA
$7FFF
Move Fractional Word to
MOVES.F
Moves.f d0,r0
MOVES.F Db,a16
304
Move Long to
MOVES.L
Memory With Scaling and Saturation AGU Operation
Moves.l d0,r0
MOVES.L Db,EA
Memory AGU Operation Assembler Syntax
MOVEU.B
Move Unsigned Byte from
Moveu.b $0053,d10
MOVEU.B a16,DR
310
Moveu.l #$fffffff8,d3
MOVEU.L
#u32 → Db
MOVEU.L #u32,Db
31IIIIIIIIIIIIIIII16
#u16 → Db3116
Moveu.w #$2345,d10.l
#u16 → Db150
MOVEU.W #u16,Db.H
Iiiiiiiiiiiiiiii Bit unsigned immediate data
#u16
Memory to a Register AGU Operation
MOVEU.W
Move Unsigned Word from
Moveu.w r7+2,d10
MOVEU.W a16,C4
318
Mpy d4,d5,d6
MPY
Da.H * Db.H → Dn
MPY Da,Db,Dn
Mpy d6,d6,d7
SC140 DSP Core Reference Manual 321
Mpyr d4,d5,d6
Mpyr
RndDa.H * Db.H → Dn
Mpyr Da,Db,Dn
Register/Memory Address Before After L6D6
$0000
324
Mpysu d4,d5,d6
Mpysu
Dc.H * Dd.L → Dn
Mpysu Dc,Dd,Dn
326
Mpyus Dc,Dd,Dn
Mpyus
Dc.L * Dd.H → Dn
328
Mpyuu d4,d5,d6
Mpyuu
Dc.L * Dd.L → Dn
Mpyuu Dc,Dd,Dn
330
Negate Dalu
NEG
Neg d3
NEG Dn
NEG Dn
No Operation Prefix
NOP
No operation
Nop
Bitwise Complement Dalu
Not
Not d4,d5
~Da → Dn
SC140 DSP Core Reference Manual 335
~DR.L → DR.L
Binary Inversion of a 16-Bit Operand BMU
Not D0.L
Not DR.L
Memory BMU Operation Assembler Syntax
NOT.W
Binary Inversion of a 16-Bit Operand
Not.w r1
Example or d3,d0
Bitwise Inclusive or Dalu
Da Dn → Dn
Or Da,Dn
SC140 DSP Core Reference Manual 341
#u16 DR.L → DR.L
Or #$0f0a,d0.l
#u16 DR.H → DR.H
Or #u16,DR.L
Or #u16,DR.L Or #u16,DR.H
OR.W #u16,SP-u5
OR.W #u16,Rn
OR.W #u16,SP+s16
OR.W #u16,a16
OR.W #u16,Rn
Or.w #$f01a,r1
346
SP 4 → Do SP 8 → SP
SP 8 → De SP 8 → SP
POP De
POP Do
Pop d3
Extension Pairs, Even Registers, and Loop Start Registers
Eeeee
NSP 4 → Do NSP 8 → ΝSP
NSP 8 → De NSP 8 → ΝSP
Popn Do
Popn d6.ed7.e
Popn De
352
Do → SP + 4 SP + 8 → SP
De → SP SP + 8 → SP
Push De
Push Do
Push d0.ed1.e
SC140 DSP Core Reference Manual 355
Do → NSP + 4 NSP + 8 → ΝSP
De → NSP NSP + 8 → ΝSP
Pushn De
Pushn Do
Pushn d0.ed1.e
Pushn De Pushn Do
Round Dalu
RND
RndDa → Dn
RND Da,Dn
Rnd d2,d1
Rnd d1,d5
RND Da,Dn
Dn3801 → Dn391
Rol d5
Dn39 → C → Dn0
ROL Dn
ROL Dn
Dn39-11 → Dn38-0
Ror d15
→ Dn39 Dn0 → C
ROR Dn
ROR Dn
SP 4 → SR SP 8 → SP → Nmid
RTE
SP 8 → PC
Instruction Words Cycles1 Type
Rte
Rted
Trap
Example rted
Return From Subroutine AGU
RTS
Rts
If RAS valid, then RAS → PC
RTS
Rtsd
Rtsd
Rtsd
Rtstk
Restore PC from Stack AGU
Cleared
Register Address Bit Name Description EMR3
Example rtstk
SP 8 → SP
Rtstkd
SP 8 → PC
Example rtstkd
Sat.f d2,d3
SAT.F
If Da $007FFFFFFF then $007FFF0000 → Dn
SAT.F Da,Dn
SAT.F Da,Dn
SAT.L Dn
SAT.L
Sat.l d6
SC140 DSP Core Reference Manual 381
Subtract With Borrow Dalu
SBC
Db Dc C → Dd
SBC Dc,Dd
SBC Dc,Dd
Subtract And Round Dalu
SBR
Sbr d3,d0
RndDn Da → Dn
0010 1010 1110 0111 0000 0000 1000$2AE7
Skipls
If LCn ≤ Then PC + displacement → PC Skipls label → LFn
Skipls label
Skipls label
Skipls label
Enter the stop processing state
Stop
Stop Stop Instruction Processing AGU Operation
Subtract Dalu
SUB
Sub d1,d0,d2
SUB #u5,Dn
Sub d0,d1,d2
SC140 DSP Core Reference Manual 391
Sub2 d0,d1
SUB2
Subtract Two 16-Bit Values Dalu
SUB2 Da,Dn
Subtract AGU
Suba
Suba r1,r0
Suba #u5,Rx
Suba
Shift Left and Subtract Dalu
Subl
Subl d0,d1
Dn Da → Dn
$0$FF Ffff Fffe
Subnc.w #$15,d0
SUBNC.W
Dn #s16 → Dn
SUBNC.W #s16,Dn
SUBNC.W #s16,Dn
Sxt.w d3,d2
Sign-Extension Dalu
Sxt.b d3,d0
Sxt.l d3
Sxta.w r3
Sign-Extension AGU
Sxta.b r3,r1
SXTA.B
Transfer Data Register to Data Register Dalu
TFR
Tfr d15,d14
Tfr d7,d6
TFR Da,Dn
Tfra r0,r1
Tfra
Rx → Rx
Tfra rx,Rx
SC140 DSP Core Reference Manual 407
If Srexp = Then NSP → Rn
To/from a Register AGU
Else ESP → Rn If Srexp = Then Rn → NSP
Else Rn → ESP
Tfra r0,osp
If T=1, then Da → Dn
Tfrt d14,d15
If T=0, then Da → Dn
Tfrt Da, Dn
Tfrt
TRAPn
Trap Execute a Software Exception AGU Trap Operation
Trap
Test for Equal to Zero Dalu
Tsteq
Tsteq d1
If Dn == 0, then 1 → T, else 0 → T
Tsteqa.w r4
TSTEQA.x Test for Equal to Zero AGU TSTEQA.x Operation
Tsteqa.l r1
TSTEQA.W Rx
TSTEQA.W TSTEQA.L
Test for Greater Than Or Equal to Zero Dalu
Tstge
Tstge d4
If Dn = 0, then 1 → T, else 0 → T
TESTGEA.L Rx
Tstgea.l r7
If Rx ≥ 0, then 1 → T, else 0 → T
TSTGEA.L Rx
Tstgt d6
Tstgt Test for Greater Than Zero Dalu Tstgt Operation
If Dn 0, then 1 → T, else 0 → Τ
Tstgt Dn
Tstgta r2
Tstgta Test for Greater Than Zero AGU Tstgta Operation
If Rx 0, then 1 → T, else 0 → Τ
Tstgta Rx
Little Endian Mode
Word Big Endian Mode
VSL
Viterbi Shift Left Move AGU
VSL.4F D2D6D1D3,Rn+N0
VSL.4W D2D6D1D3,Rn+N0
VSL.2W D1D3,Rn+N0
VSL.2F D1D3,Rn+N0
After Big Endian
Vsl.2w d1d3,r0+n0
After Little Endian
VSL.4W
Wait
Enters the low-power standby Wait processing
State
Response
Wait
Zxt.w d3,d6
Zero Extension Dalu
Zxt.b d2,d5
Zxt.l d0
Zxta.w r4
Zero Extension AGU
Zxta.b r3,n2
ZXTA.B
ZXTA.x 432
Appendix B StarCore Registry
Using the StarCore Registry
Set Version SoC / platform
Table B-1. Scid Assignments
Hex Bits Instruction Cores Example
Index
Ecnten
Eeddef
Eselctrl 4-26ESELDI 4-26ESELDM 4-26ESELDTB 4-26 Eseletb
MOVES.F A-299 MOVES.L A-301 MOVEU.B A-307
Macsu A-239 Macus A-241 Macuu A-243
Mpysu A-325 Mpyus A-327 Mpyuu A-329
Rtstk A-374
Index
Index
SC140 DSP Core Reference Manual
