Freescale Semiconductor SC140 specifications Memory Access Timing

Instruction Timing

Table 5-8. Number of Cycles Needed by Change-of-Flow Instructions (Continued)

Instruction	Number of	Minimum Number	Condition
	Cycles	of Cycles
RTE	5		Shadow SP is valid.
	6		Shadow SP is not valid.
RTED	5 – Cd		Shadow SP is valid.
	6 – Cd		Shadow SP is not valid.
RTS	3		RAS is valid.
	5		RAS is not valid and shadow SP is valid.
	6		RAS is not valid and shadow SP is not valid.
RTSD	3 – Cd	1	RAS is valid and shadow SP is valid.
	3 – Cd	2	RAS is valid and shadow SP is not valid.
	5 – Cd		RAS is not valid and shadow SP is valid.
			RAS is not valid and shadow SP is not valid.
	6 – Cd
RTSTK	5		Shadow SP is valid.
	6		Shadow SP is not valid.
RTSTKD	5 – Cd		Shadow SP is valid.
	6 – Cd		Shadow SP is not valid.
SKIPLS	4		Jump is taken.
	1		Jump is not taken.
BREAK	4
CONT	3		SA is taken.
	4		Destination is taken.
CONTD	3 – Cd	1	SA is taken.
	4 – Cd	1	Destination is taken.
TRAP	5

5.3.3 Memory Access Timing

The SC140 core executes up to one execution set per cycle. The programmer can specify up to two memory MOVE instructions per execution set. Since the memory interface has one program and two data buses, up to three simultaneous memory accesses can occur as described in Section 2.4, “Memory Interface.”

The memory organization determines when memory contention occurs for simultaneous accesses. There is likely contention if the same byte-addressed location is accessed. However, there could be a contention in other cases, due to the memory internal structure. Because memory is not implemented to provide true multi-port access, accessing of two different addresses in the same memory block may cause a contention. The intent of the following section is to describe the timing for memory accesses generated by instructions in the same execution set. In some examples, no problems arise since the memory accesses fall into different cycles. In other examples, memory contention can occur.

SC140 DSP Core Reference Manual 5-21