Freescale Semiconductor SC140 Real-Time Data Transfer, General EOnCE Register Issues

EOnCE Register Addressing

The ACK bit could be checked on TDO by executing a “neutral” JTAG EOnCE command such as “ENABLE_EONCE”. Only after it was verified with the ACK bit that the previous access was accepted by the core, the next register could be accessed. This check should be performed also for accessing the ECR.

4.6.3 Real-Time Data Transfer

The EOnCE controller enables the core software to transmit data from the core to the host as well as to receive data sent from the host to the core. This is done by means of a simple receive or transmit mechanism while the core is running.

For transmitting data to the host, the core writes to the transmit register ETRSMT by means of a move instruction using the memory-mapped address of the ETRSMT register. The TRSMT status bit in the ESR is asserted by the EOnCE (see Section 4.7.2, “EOnCE Status Register (ESR),” for more details). The host can poll the TRSMT status bit to see when the data in the ETRSMT register is available. Or alternatively, the host can program the EE4 signal to reflect this status bit externally for interrupt-like transfers, and then read the ETRSMT through TDO using the mechanism described in Section 4.7.1, “EOnCE Command Register (ECR).” The TRSMT bit is cleared by the EOnCE automatically after the ETRSMT register is read by the host. A debug exception can be generated to notify the core that the register can be written again.

The ERCV register can be used for receiving data from the host. The host writes to the ERCV register through the TDI input signal. The EOnCE automatically sets the status bit RCV in the ESR. For more information, see Section 4.7.2, “EOnCE Status Register (ESR).” This bit can be polled by the core to see when the data is ready in the ERCV register, or the application can configure EOnCE to generate a debug exception when the data is ready in the ERCV register. See Section 4.7.4, “EOnCE Receive Register (ERCV),” for more information. The RCV bit is automatically cleared by the EOnCE after the ERCV register is read by the core.

4.6.4 General EOnCE Register Issues

During core reset, the following takes place:

•The selector mask registers are written with zeros.

•All others mask registers are written with ones.

•The EE_CTRL register is written with ones.

•All the remaining registers in the EOnCE programming model are written with zeros.

Only one EOnCE register could be accessed per VLES. It is not allowed to group together a read access from the EOnCE in parallel with an instruction that performs a memory write.

Reserved or unused bits in all registers should be written as zero and the read value should be masked. Writing to unimplemented registers has no effect in the current implementation, but should be avoided for future software compatibility. Reading from unimplemented or write-only registers as well as reading the most significant bits (MSBs) of an 8-bit or 16-bit register with a 32-bit MOVE instruction are both illegal and produces undefined results.

Software write access is possible only if the SWDIS bit in the EMCR register is cleared. The only exception is the ETRSMT register that can always be written by software. When the SWDIS bit is set, read-only access is enabled except reading from the trace buffer.

If the software writes and then reads a given EOnCE register, a NOP or other instruction must be inserted before the read instruction in order to read back the value just written.

4-34 SC140 DSP Core Reference Manual