Moves.4f d0d1d2d3,r0, DaDbDcDd → EA | Freescale Semiconductor SC140

MOVES.4F

MOVES.4F Move Four Fractional Words to MOVES.4F

Memory With Scaling and Saturation (AGU)

Operation	Assembler Syntax
Da:Db:Dc:Dd → (EA)	MOVES.4F Da:Db:Dc:Dd,(EA)

Description

The data that is moved from each register to memory is scaled according to the scaling mode. If the Ln bit is set, it is also saturated. The address register values must be quad word-aligned (a multiple of 8). This instruction is affected by by SM (Saturation Mode bit - SR[2]). When SM is set, scaling is not performed, and the scale bits S[1:10] have no effect.

MOVES.4F Da:Db:Dc:Dd,(EA)

Writes four signed fractional words from a data register quad to memory addresses pointed to by an address register with an optional offset or post-increment.

The first operand (Da) will be moved to the lower memory address (EA). The second operand (Db) will be moved to memory address (EA + 2). The third operand (Dc) will be moved to memory address (EA + 4). And, the fourth operand (Dd) will be moved to memory address (EA + 6). In order to keep this behavior in both big endian and little endian modes, the core will drive the data bus differently in each mode. See Section 2.4.1, “SC140 Endian Support,” on page 2-56, for more detail on bus and memory behavior for each mode.

Status and Conditions that Affect Instruction

Register Address	Bit Name	Description
MCTL[31:0]	AM3–AM0	Address modification bits when updating R0–R7. Otherwise, the
		instruction is not affected by MCTL.
SR[5:4]	S[1:0]	Scaling mode bits choose: no scaling, scale up one bit, or scale
		down one bit.
Ln	L	Limited values are written to the destination if the Ln bit is set.
EMR[16]	BEM	Set if big endian mode, cleared if little endian mode.

Status and Conditions Changed by Instruction

Register Address	Bit Name	Description
SR[6]	S	Scaling bit, set when the absolute value of any one of the words
		moved (after scaling and limiting) is greater than or equal to 0.25
		and less than 0.75.

Example