Freescale Semiconductor SC140 specifications Hardware Loops, Loop Programming Model

Hardware Loops

5.4 Hardware Loops

One of the most important features of a DSP algorithm is efficient loop execution. The SC140 core has a fully optimized looping mechanism, which enables loop execution with up to four levels of loop nesting. The loop programming model is part of the PSEQ programming model, and includes four pairs of registers that specify the start address of the loop as well as the number of times the loop is to be executed.

5.4.1 Loop Programming Model

There are four pairs of loop registers with two registers in each pair:

•Loop start address registers (SA0, SA1, SA2, SA3)

•Loop counter registers (LC0, LC1, LC2, LC3)

Each pair is responsible for a single hardware loop. The functionality of each register pair is described in the sections that follow.

Figure 5-4 shows the hardware loop programming model. This programming model holds the full loop state and can be saved and restored for exception service routines, context switches, or spill/fill operations to support additional nesting levels.

31 0 31 0

SA0

SA1

SA2

SA3

			LC0
31	0		LC1		31					0
31	0		LC2		31					0
31	0		LC3		31					0
	LOOP START					LOOP COUNTER
	ADDRESS REGISTERS						REGISTERS
			31			30	29		28	27
		SR		SLF		LF3		LF2	LF1	LF0

STATUS

REGISTER

Figure 5-4. Hardware Loop Programming Model

5.4.1.1 Loop Start Address Registers (SAn)

The SAn registers are 32-bit read/write registers that are used to define the address of the first execution set in each loop. The DOSETUPn label instruction initializes the SAn register with the start address. The LOOPSTARTn assembly directive also marks the start address and must be placed at the same address as the label of the DOSETUPn instruction.

SC140 DSP Core Reference Manual 5-25