Freescale Semiconductor SC140 ISAP-core register transfers, Example 6-1. Isap memory access

ISAP-core register transfers

However, this feature requires some assembler support (core and ISAP) when using such instructions. When the ISAP must either write or retrieve data from the data memory via the data busses, the core assembler must create a parallel AGU MOVE instruction in the same VLES as the ISAP instruction.

This method works as follows:

When the assembler encounters an ISAP data move instruction, the core assembler creates an AGU MOVE instruction that will generate the required address to the data memory.

Example 6-1. ISAP memory access

To understand this, look at the following lines of code:

core_ins {move_special k0,(r1)}

In this example, two parallel instructions are used:

1st - core_ins = a generic core instruction

2nd - {move_special k0, (r1)} = a fictional ISAP instruction (for illustration purposes only), whose intent is to take the data in k0 (an ISAP register), and place it in the address whose value is found in the core register r1

The core assembler translates the above line of code (at the opcode level) to read, in effect, the following:

core_ins move.l d0,(r1) {move_special k0,data bus}

In order for this to work, the core must not drive d0 to the memory. The core hardware achieves this in the following way: A memory MOVE instruction that uses a DALU register (D0 to D15) in parallel to any ISAP instruction simply will not drive or sample the D register. In effect, the d0 in this instruction becomes a dummy source which the core therefore ignores, and in our case only the address found in r1 is driven to on the data address bus. In a complementary manner, the ISAP move_special instruction only drives the data in k0 on the appropriate data bus, and not handle the addressing of the access.

In this manner, the data memory receives data from the ISAP, and the address from the AGU of the core.

There are some ramifications of this method of memory access, that are mentioned in Section 6.8.4, “Sequencing rules for T bit update.” .

The ISAP must support both big and little endian byte order conventions in the same manner as the core supports these conventions (see Section 2.4.1, “SC140 Endian Support,” ).

6.5 ISAP-core register transfers

The ISAP architect can define ISAP instructions that exchange data between core and ISAP registers. These instructions are treated in a similar manner to MOVE instructions. That is, the core assembler translates the ISAP instructions into two equivalent instructions: one core instruction that drives or samples the core register, and an ISAP instruction that samples or drives the ISAP register.

The assembler uses the core instruction “MOVE.L C4<->Db” (See Appendix A, Appendix , “MOVE.L,” on page A-275). When executed in parallel with an ISAP instruction, the core does not drive or sample the “Db” (DALU) register. This enables the core to perform data transfers between the C4 registers (D, R, N, B, M) and ISAP registers.

SC140 DSP Core Reference Manual 6-61