Freescale Semiconductor SC140 specifications Shows a block diagram of the event counter

EOnCE Module Internal Architecture

Figure 4-9 shows a block diagram of the event counter.

Count Value

System Clock

Inst Execution

Event0-5

EventD

Trace

DEBUGEV

EC0-1

External EDCA6,7 event

Count

Selector

Control Register

ECNT_CTRL

31-bit

Event

Counter

ECNT_VAL

31-bit

Extension Counter

ECNT_EXT

Count Event

Figure 4-9. Event Counter Block Diagram

ECNT_VAL and ECNT_EXT are 32-bit registers, but their values are limited to 31 bits; their MSB is always zero. Their range is from zero to $7FFF FFFF. The counter counts down, while the extension counter counts up. The event counter has two counting modes:

•Single count: The counter counts down to zero, and then disables. Upon reaching zero, an EOnCE event is generated (the outcome depends on the event selector).

•Extended count: When the counter reaches zero, it wraps around to $7FFF FFFF and continues to count. The extension counter is incremented. No EOnCE event is generated.

Table 4-7 shows the event counter register set.

Table 4-7. Event Counter Register Set

Register Name	Description
ECNT_CTRL	Event counter control register
ECNT_VAL	Event counter value register (32-bit)
ECNT_EXT	Extension counter value register (32-bit)

The functionality of the event counter registers is described in Section 4.8, “Event Counter Registers.”

SC140 DSP Core Reference Manual 4-19