Freescale Semiconductor SC140 specifications Event Selector Mask Debug Exception Register Eseldi

Event Selector (ES) Registers

4.10.3Event Selector Mask Debug Exception Register (ESEL_DI)

This 16-bit register has one bit for each source of event selection. Setting the appropriate bit enables the related source to cause a debug exception.

Figure 4-25 displays the bit configuration of ESEL_DI.

	BIT 15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	BIT 0
	DEBUGE	EE4	EE3	EE2	EE1	EE0	COUNT	EDCD	EDCA	EDCA	EDCA	EDCA	EDCA	EDCA	EDCA	EDCA
	V								7	6	5	4	3	2	1	0
TYPE	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
RESET	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Figure 4-25. Event Selector Mask Debug Exception (ESEL_DI)

If multiple sources are configured to cause a debug exception, they are ANDed or ORed according to the value of the SELDI bit in the ESEL_CTRL. For more information, see Section 4.10.1, “Event Selector Control Register (ESEL_CTRL).” If all the bits are set to zero, the ES does not issue a debug exception.

4.10.4Event Selector Mask Enable Trace Register (ESEL_ETB)

This 16-bit register has one bit for every source of the ES. Setting the appropriate bit configures the related source to enable trace.

Figure 4-26 displays the bit configuration of ESEL_ETB.

	BIT 15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	BIT 0
	DEBUGE	EE4	EE3	EE2	EE1	EE0	COUN	EDCD	EDCA	EDCA	EDCA	EDCA	EDCA	EDCA	EDCA	EDCA
	V						T		7	6	5	4	3	2	1	0
TYPE	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
RESET	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Figure 4-26. Event Selector Mask Enable Trace (ESEL_ETB)

If multiple sources are configured to enable trace, they are ANDed or ORed according to the value of the SELETB bit in the ESEL_CTRL. If all the bits are set to zero, the ES does not enable trace.

The same event cannot be configured to both enable and disable tracing.

4-64 SC140 DSP Core Reference Manual