Freescale Semiconductor SC140 specifications Sequencing Rules, Register Read/Write

Programming Rule Notation

7.4.2 Sequencing Rules

Sequencing rules enforce the VLES sequencing semantics by specifying the minimum distance between different VLES having instructions “A” and “B”. They use the notation “at least n VLES are required between” or “the minimum number of VLES between” instructions “A” and “B”. For a minimum VLES distance between “A” and “B”, the VLES having “A” and “B” are not included in this count.

7.4.2.1 Cycle Counts

Rules A.1 and A.2 specify a minimum cycle distance between “A” and “B” events. They use the notation “at least n cycles are required between when A and when B” occur. This takes into account the exact pipeline stages when “A” and “B” occur. By grouping a multiple cycle instruction with “A”, the minimum cycle distance may be met without scheduling additional VLES between “A” and “B”. For a minimum cycle distance between “A” and “B”, the cycles when “A” and “B” occur are not included in this count.

7.4.2.2 Conditional Execution

If instructions “A” or “B” are conditional or conditioned by an IFc instruction, they will execute only if their execution condition is true. If “A” and “B” have mutually exclusive execution conditions, their execution cannot violate a sequencing rule. The simulator knows if “A” and “B” execute from its simulation trace, and detects programming rules considering their conditional execution. However, the assembler cannot know the T bit state when “A” or “B” execute. So the assembler detects sequencing rules independent of conditional execution. That is, it assumes all conditional instructions always execute.

7.4.2.3 Simulator Execution Counts

A conditional VLES that is not executed (becomes a NOP) is counted by the simulator as one VLES for VLES-based sequencing rules. For cycle-based sequencing rules, a conditional VLES that is not executed (becomes a NOP) is counted by the simulator as one cycle.

7.4.3 Register Read/Write

In this chapter the programming rules use the notation “read” and “write” to refer to whole register sources and destinations, respectively. This notation applies to instruction source and destination operands, both explicit and implicit (implied), as specified in each instruction definition in Appendix A.2, “Instructions,” on page A-19.

7.4.3.1 Register Names

Some rules apply to selected registers — address, data, or program control. The rules specify the registers using the names given in Table A-3: Register Abbreviations on page A-3.

7-4 SC140 DSP Core Reference Manual