Freescale Semiconductor SC140 specifications Instruction Word Transfers

Memory Interface

2.4.1.5 Instruction Word Transfers

Instruction words are transferred to the core from memory over the program data bus (PDB) to special instruction registers in the program dispatch unit (PDU).

The instruction registers can be accessed only with aligned access of 128-bit width (8 instruction words). Figure 2-24 shows the program memory organization in big and little endian modes. Note that program data consists of a series of 16-bit instructions. In this example the assembler determines the instructions to be:

word address $00 instruction $a0b0 word address $02 instruction $c0d0 word address $04 instruction $e0f0 word address $06 instruction $a1b1 word address $08 instruction $c1d1 word address $0a instruction $e1f1 word address $0c instruction $a2b2 word address $0e instruction $c2d2 word address $10 instruction $e2f2

.....

These are to be placed in memory as shown in the following figure.

		Big Endian									Little Endian
0	1	2	3	4	5	6	7		7	6	5	4	3	2	1	0
a0b0		c0d0		e0f0		a1b1		0	a1b1		e0f0		c0d0		a0b0		0
c1d1		e1f1		a2b2		c2d2		8	c2d2		a2b2		e1f1		c1d1		8
e2f2		a3b3		c3d3		e3f3		16 ($10)	e3f3		c3d3		a3b3		e2f2		16 ($10)
								24 ($18)									24 ($18)

Figure 2-24. Program Memory Organization in Big and Little Endian Modes

The assembler outputs a byte stream to the loader and therefore corrects for the byte address reversal inside each 16-bit instruction to achieve the memory results above.

Big Endian Assembler OutputLittle Endian Assembler Output byte address $00 data $a0byte address $00 data $b0

byte address $01 data $b0byte address $01 data $a0 byte address $02 data $c0byte address $02 data $d0 byte address $03 data $d0byte address $03 data $c0 byte address $04 data $e0byte address $04 data $f0

..... .....

2-62 SC140 DSP Core Reference Manual