Freescale Semiconductor Stack Support, Loop Timing, 1 SC140 Single Stack Memory Use

Stack Support

5.4.7 Loop Timing

If the loop starting address is not aligned (meaning that the first execution set is spread over two fetch sets), one stall cycle is added to the loop execution on each iteration of the loop. In every other case, no stall cycles are added to the loop execution time. A loop may be aligned with the assembler directive FALIGN, which when placed just before the LOOPSTART, will cause the assembler to insert NOP instructions in order to align the first execution set of the loop.

At the end of a long loop having LCn greater than one, decoding a LPMARKB bit does not cause a stall. Whereas decoding a LPMARKA bit in the same situation, adds the change-of-flow stall cycles.

5.5 Stack Support

Multitasking creates the impression that the DSP is executing several tasks concurrently, when in reality it is only executing a single task at any given time. The SC140 core has many features that help software designers implement a software stack, and more efficiently support a multitasking real time operating system (RTOS). These features include:

•Two stack pointers: one for the normal stack (NSP) and one for the exception stack (ESP), only one of which is active at a time (referenced as SP)

•Separate user/normal and exception working modes

•Push and pop instructions

•Stack-oriented addressing modes

5.5.1 SC140 Single Stack Memory Use

In a single stack pointer system, each task stack must allocate memory for RTOS function calls and interrupts. Thus, extra memory is allocated on each task stack as shown in Figure 5-6.

Task

Task

Task

SP

SP

SP

Task Stack Task Stack Task Stack

Extra space allocated for RTOS

Extra space allocated for interrupts

Figure 5-6. SC140 Memory Use with a Single Stack Pointer

The memory space for interrupts is replicated on each task stack since any task can be interrupted. The interrupt functions can use the stack for subroutines, local variables, and so on. So each task stack must be increased by the size of the maximal interrupt memory use.

5-32 SC140 DSP Core Reference Manual