2-6 SC140 DSP Core Reference Manual
DALU
2.2 DALU
This section describes the architecture and operation of the DALU, the block where most of the arithmetic
and logical operations are performed on data operands. In addition, this section details the arithmetic and
rounding operations performed by the DALU as well as its programming model.
2.2.1 DALU Architecture
The DALU performs most of the arithmetic and logical operations on data operands in the SC140 core.
The data registers can be read from or written to memory over the XDBA and the XDBB as 8-bit, 16-bit,
or 32-bit operands. The 64-bit wide data buses, XDBA and XDBB, support the transfer of several operands
in a single access. The source operands for the DALU, which may be 16, 32, or 40 bits, originate either
from data registers or from immediate data. The results of all DALU operations are stored in the data
registers.
All DALU operations are performed in one clock cycle. Up to parallel arithmetic operations can be
performed in each cycle. The destination of every arithmetic operation can be used as a source operand for
the operation immediately following without any time penalty.
The components of the DALU are as follows:
•A register file of sixteen 40-bit registers
•Four parallel ALUs, each containing a MAC unit and a BFU with a 40-bit barrel shifter
•Eight data bus shifter/limiters that allow scaling and limiting of up to four 32-bit operands
transferred over each of the XDBA and XDBB buses in a single cycle
Figure 2-2 shows the architecture of the DALU.
Figure 2-2. DALU Architecture
Memory Data Bus 1 (XDBA)
Memory Data Bus 2 (XDBB)
64 64 64 64
(8) Shifter/Limiters
Data Registers D0–D15
40 40
40
40
4040 40 40 40 40 40
ALU
40 40 40
40 40 40 40 40 40
ALUALU ALU