1-2 SC140 DSP Core Reference Manual
Architectural Differentiation
1.2 Architectural Differentiation
The SC140architecture differentiates itself in the market with the following capabilities:
• High-level Abstraction of the Application Software
— DSP applications and kernels can currently be developed in the C programming language. An
optimizing compiler generates parallel instructions while maintaining a high code density.
— An orthogonal instruction set and programming model along with single data space and byte
addressability enable the compiler to generate efficient code.
— Hardware supported integer and fractional data types enable application developers to choose
their own style of code development, or to use coding techniques derived from an
application-specific standard.
• Scalable Performance
— The number of execution units is independent of the instruction set, and can be tailored to the
application’s performance requirement. The SC140 contains four arithmetic logic un its (ALUs)
and two address arithmetic units (AAUs).
— A high frequency of operation is achieved at low voltage, providing four million multiply and
accumulate (MAC) operations per second (4 MMACS) for each megahertz of clock frequency.
— Support exists for application-specific accelerators, providing a performance boost and
reduction in power consumption.
• High Code Density for Minimized Cost
— 16-bit wide instruction encoding.
— A rich and orthogonal instruction set, major portions of which focus on control code that can
often occupy most of the application code.
— Variable length execution set (VLES) for DSP kernel operations.
• Improved Support for Multi-tasking Applications
— Dual stack pointer support in HW.
• Optimized Power Management Control
— Very low power consumption.
— Low voltage operation.
— Power saving modes.
• Efficient Memory and I/O Interface
— Very large on-chip zero-wait state static random access memory (SRAM) capability.
— Support for slower on-chip memory via wait-states.
— 32-bit address space for both program and data (byte-addressable).
— Unified data and program memory space.
— Decoupled external memory timing with independent clock.
• Core Organization and Design
— Supports flexible system-on-a-chip (SoC) configurations.
— Portable across fabrication lines and foundries.